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US 8,428,212 B2Granted
Frequency synthesis using upconversion PLL processes
AssigneeIntel Mobile Communications GmbH
InventorsChristian Grewing, Stefan van Waasen
Life of this patent
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Abstract
Techniques for frequency synthesis using upconversion PLL processes are described herein.
Claims20
A circuit, comprising:
- a frequency-locked loop portion configured to receive an input frequency and to generate an upconverted intermediate frequency and a frequency information indicative of a needed frequency correction of a frequency-locked loop output frequency;
- an intermediate portion configured to receive the upconverted intermediate frequency and a reference frequency, and further configured to provide an intermediate output that is either the upconverted intermediate frequency or the reference frequency;
- and
- a phase-locked loop portion configured to receive the intermediate output and to generate a phase-locked output frequency based on the frequency information.
1 more element
An electronic device, comprising:
- a processor;
- and
- a communication component operatively coupled to the processor and configured to at least one of receive and transmit communication signals, the communication component including a frequency synthesizer component having:
- a frequency-locked loop portion configured to receive an input frequency and to generate an upconverted intermediate frequency and a frequency information indicative of a frequency correction;
- an intermediate portion coupled to the frequency-locked loop portion and configured to receive the upconverted intermediate frequency and a reference frequency, and further configured to provide an intermediate output that is either the upconverted intermediate frequency or the reference frequency;
- and
- a phase-locked loop portion coupled to the intermediate portion and configured to receive the intermediate output and to generate a phase-locked output frequency based on the frequency information.
4 more elements
A method, comprising:
- receiving a low frequency input;
- providing an upconverted intermediate signal;
- providing a frequency information indicative of a frequency correction;
- selecting one of the upconverted intermediate signal and a high frequency reference;
- and
- frequency-locking the selected upconverted intermediate signal or the high frequency reference based on the frequency information to provide an upconverted phase-locked output.
3 more elements
Dependencies are inferred from the claim text.