Lock detection circuit and method for phase locked loop system
AssigneeVIA Technologies, Inc.
InventorChun-Che Huang
Life of this patent
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Abstract
A lock detection circuit and method are disclosed for phase locked loop (PLL) systems. The lock detection circuit primarily includes a delay unit and an asserting logic unit. The delay unit receives the phase error signal of the PLL and produces a present phase error signal, and then accordingly generates at least one delayed phase error signal. The asserting logic unit generates an unlock indicating signal (UNLOCK) according to the present phase error signal and the delayed phase error signal. A phase lock indicating signal will be asserted if the unlock indicating signal is not asserted within a predetermined number of counting pulses.
Claims23
A lock detection circuit for a phase locked loop system (PLL), comprising:
- a delayed unit receiving a phase error signal from the phase locked loop system to generate a present phase error signal, and then generating a plurality of delayed phase error signals according to the present phase error signal;
- a selecting unit that according to a designated phase error tolerance selecting one of the plurality of delayed phase error signals from the plurality of delayed phase error signals ;
- and
- a logic asserting unit providing an unlock indicating signal according to the present phase error signal and the selected one of the plurality of delayed phase error signals, wherein the phase error signal is generated according to the unlock indicating signal.
A lock detection circuit for a phase locked loop system, comprising:
- an input clock error detection logic unit, generating a phase error signal according to a reference clock signal, an unlock indicating signal, and a divided voltage controlled oscillator (VCO) clock signal of the phase locked loop system;
- a sampling logic unit, generating a present phase error signal according to the phase error signal, and then generating a plurality of delayed phase error signals according to the present phase error signal, and then providing the unlock indicating signal according to the present phase error signal and the selected one of the plurality of delayed phase error signals, wherein the one of the plurality of delayed phase error signals is selected according to a designated phase error tolerance from the plurality of delayed phase error signals;
- and
- a counting logic unit, configured to count pulses of the reference clock signal and assert a phase lock indicating signal if the unlock indicating signal is not asserted within a predetermined number of the pulses of the reference clock signal.
A lock detection method for a phase locked loop system, comprising:
- generating a phase error signal according to a reference clock signal, an unlock indicating signal, and a divided voltage controlled oscillator (VCO) clock signal of the phase locked loop system;
- generating a present phase error signal according to the phase error signal, and generating a plurality of delayed phase error signals according to the present phase error signal;
- providing the unlock indicating signal according to the present phase error signal and one of the plurality of delayed phase error signals,
- selecting the one of the plurality of delayed phase error signals according to a designated phase error tolerance from the plurality of delayed phase error signals ;
- and
- counting pulses of the reference clock signal and asserting a phase lock indicating signal if the unlock indicating signal is not asserted within a predetermined number of the pulses of the reference clock signal.
Dependencies are inferred from the claim text.