System and method for determining a time for safely sampling a signal of a clock domain

A method, comprising;

• calculating a frequency estimate of a first clock domain utilizing a frequency estimator;
• calculating a phase estimate of the first clock domain based on the frequency estimate, utilizing a phase estimator;
• and
• determining a time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate;
• wherein a FIFO synchronizer is realized by using a plurality of even/odd synchronizers to pass a tail pointer into an output clock domain and a head pointer into an input clock domain;
• wherein an even tail pointer, an odd tail pointer, an even head pointer, and an odd head pointer are utilized by:
• computing the even tail pointer on even clock cycles of an input clock and the odd tail pointer on odd clock cycles of the input clock, and
• storing the computed even tail pointer in an even tail register on the even clock cycles of the input clock and the computed odd tail pointer in an odd tail register on the odd clock cycles of the input clock.

A system, comprising:

• a frequency estimator for calculating a frequency estimate of a first clock domain;
• and
• a phase estimator for calculating a phase estimate of the first clock domain based on the frequency estimate;
• wherein the system is operable such that a time during which a signal from the first clock domain is unchanging is determined, using the phase estimate, such that the signal is capable of being safely sampled by a second clock domain;
• wherein the system is operable such that the first clock domain successively writes to a plurality of registers on successive cycles and the second clock domain uses the phase estimate to select a most recently written one of the registers that is safe to sample in the second clock domain.

A system, comprising:

• a frequency estimator for calculating a frequency estimate of a first clock domain;
• and
• a phase estimator for calculating a phase estimate of the first clock domain based on the frequency estimate;
• wherein the system is operable such that a time during which a signal from the first clock domain is unchanging is determined, using the phase estimate, such that the signal is capable of being safely sampled by a second clock domain;
• wherein the system is operable such that a FIFO synchronizer is realized by using a plurality of even/odd synchronizers to pass a tail pointer into an output clock domain and a head pointer into an input clock domain;
• wherein the system is operable such that an even tail pointer, an odd tail pointer, an even head pointer, and an odd head pointer are utilized by:
• computing the even tail pointer on even clock cycles of an input clock and the odd tail pointer on odd clock cycles of the input clock, and
• storing the computed even tail pointer in an even tail register on the even clock cycles of the input clock and the computed odd tail pointer in an odd tail register on the odd clock cycles of the input clock.