Equalizing receiver

An integrated circuit adapted to receive an incoming electrical signal and to generate therefrom a sequence of digital values, the integrated circuit comprising:

• a buffer operable to receive and sequentially store digital values in the sequence;
• an equalization circuit coupled to the buffer, operable to generate a compensation signal in dependence upon the state of at least one digital value from the buffer, and operable to equalize the incoming electrical signal in dependence upon the compensation signal;
• and
• a partial response circuit including at least two comparators that are each operable to concurrently compare the equalized signal against respective thresholds to produce at least two respective comparisons corresponding to each digital value in the sequence, the partial response circuit operable to select between the at least two respective comparisons to produce each corresponding digital value in the sequence in dependence on a state of a prior digital value in the sequence;
• wherein the partial response circuit includes a latch operable to store the prior digital value, and wherein the buffer is coupled to the latch and is operable to receive each digital value in the sequence therefrom.

An equalizing receiver adapted to receive an incoming electrical signal and to generate therefrom a sequence of digital values, the equalizing receiver comprising:

• a decision feedback equalization circuit operable to equalize the incoming electrical signal in dependence on a compensation signal to generate an equalized signal, the compensation signal dependent on at least one previously-received digital value in the sequence;
• and
• a partial response circuit coupled to the decision feedback equalization circuit to receive the equalized signal and operable to generate therefrom the sequence of digital values, the partial response circuit operable to compare the equalized signal against at least two different decision thresholds to produce at least two respective comparisons, and to select between the at least two respective comparisons for each digital value in the sequence in dependence on a state of a least latent prior digital value in the sequence;
• wherein each value of the at least one previously-received digital value represents greater latency than the least latent digital value in the sequence.

An equalizing receiver adapted to receive an incoming electrical signal and to generate therefrom a sequence of digital values, the equalizing receiver comprising:

• means for generating a compensation signal dependent on at least one previously-received digital value in the sequence and for equalizing the incoming electrical signal in dependence on a compensation signal, to generate an equalized signal;
• and
• means for comparing the equalized signal against at least two different decision thresholds to produce at least two respective comparisons, and for selecting between the at least two respective comparisons for each digital value in the sequence in dependence on a state of a prior digital value in the sequence;
• wherein the at least one previously-received digital value does not include the prior digital value.

An integrated circuit adapted to receive an input signal that conveys a sequence of bits, the integrated circuit comprising:

• a first sampler operable to sample the input signal using a first threshold and to produce a first conditional sample representing logic state of a current bit;
• a second sampler operable to sample the input signal using a second threshold and to produce a second conditional sample representing the logic state of the current bit;
• a circuit operable to receive the first and second conditional samples and to select one of the first and second conditional samples as an output signal as a function of the logic state of a first prior bit;
• and
• a decision feedback equalizer operable to modify the analog voltage of the input signal using weighted feedback dependent on the logic state of a second prior bit.