Methods and apparatus for detecting and decoding adaptive equalization training frames

An apparatus for detecting a training frame in received data, said training frame comprised of a frame marker having a string of a predefined length of binary ones and a string of a predefined length of binary zeroes, said apparatus comprising:

• means for shifting said received data by one or more bit positions;
• means for inserting at least one predefined binary value at one end of said shifted received data to generate a modified version of said received data;
• a logic circuit for processing said received data and said modified version of said received data, wherein said received data and said modified version of said received data each comprise a plurality of bits and wherein said logic circuit identifies when corresponding bit positions in said received data and said modified version of said received data have different values;
• and
• a frame marker detector that identifies said training frame when an output of said logic circuit has a first binary value in an approximate middle of a predefined number of a second binary value, wherein said output comprises a bit position corresponding to each of said plurality of bits.

An apparatus for detecting a training frame in received data, said training frame comprised of a frame marker having a string of a predefined length of binary ones and a string of a predefined length of binary zeroes, said apparatus comprising:

• a data shifting circuit for shifting said received data by one or more bit positions;
• a bit generator for inserting at least one predefined binary value at one end of said shifted received data to generate a modified version of said received data;
• a logic circuit for processing said received data and said modified version of said received data, wherein said received data and said modified version of said received data each comprise a plurality of bits and wherein said logic circuit identifies when corresponding bit positions in said received data and said modified version of said received data have different values;
• and
• a frame marker detector that identifies said training frame when an output of said logic circuit has a first binary value in an approximate middle of a predefined number of a second binary value, wherein said output comprises a bit position corresponding to each of said plurality of bits.