Motion search apparatus in video coding
AssigneeNippon Telegraph and Telephone Corporation
InventorsKoyo Nitta, Hiroe Iwasaki, Jirou Naganuma
Life of this patent
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Abstract
In motion search using a PE array, a technique is provided for enabling high-speed calculation while avoiding bank conflict without increasing a memory for storing pixels outside the screen. When pieces of pixel data of a plurality of lines to be read from the memory 3 (reference image memory 30) exist in a same bank, the conflict bank anticipatory read control unit 10 reads pixel data of a line in advance, and a read data holding circuit 20 holds the data until timing for inputting to a PE array unit 4. Accordingly, bank conflict can be avoided when reading pixel data from the memory 3, so that smooth pipeline processing by the PE array unit 4 can be realized.
Claims4
A motion search apparatus for use in video coding, comprising:
- a PE array unit configured to calculate a sum of absolute difference between an original image and a reference image by performing calculation in parallel using a plurality of processor elements;
- a memory configured to store pixel data of the reference image that is a target for motion search;
- a memory read unit configured to read pixel data of the reference image from the memory;
- a pixel permuting unit configured to permute the pixel data read from the memory and input the pixel data to the PE array unit;
- an evaluation unit configured to detect and evaluate a motion vector in a predetermined search range of the reference image based on the sum of absolute difference calculated by the PE array unit;
- and
- a control unit configured to control motion search by each of the units,
- the memory read unit comprising a conflict bank anticipatory read control unit configured to perform control for, when a region of the target of the motion search is outside the reference image so that pieces of pixel data of a plurality of lines to be input to the PE array unit simultaneously are stored in a same bank in the memory, reading pixel data of one line of the plurality of lines from the memory at a timing earlier than a timing required for inputting to the PE array unit, and
- the pixel permuting unit comprising a read data holding circuit configured to hold the pixel data of the line read by the memory read unit at the timing earlier than the timing required for inputting to the PE array unit until timing for inputting to the PE array unit.
Dependencies are inferred from the claim text.