Image decoding device with parallel processors

A video decoding method that performs decoding processing on blocks of a compressed video stored in a memory together with reference pictures, the decoding processing including motion compensation processing, the video decoding method comprising:

• a compensation step for sequentially performing the motion compensation processing block by block with reference to reference pictures stored in an input buffer, wherein (i) the reference pictures stored in the input buffer are one or more of the reference pictures stored in the memory and (ii) the input buffer has a capacity that sufficiently stores reference pictures corresponding to two blocks;
• and
• a reference picture transferring step for sequentially transferring reference pictures corresponding to two adjacent blocks from the memory to the input buffer utilized by the compensation step such that (i) reference pictures corresponding to a first block from among the two adjacent blocks are transferred during a first two consecutive predetermined time periods and (ii) reference pictures corresponding to a second block from among the two adjacent blocks are transferred during a second two consecutive predetermined time periods,
• wherein the first two consecutive predetermined time periods and the second two consecutive predetermined time periods overlap each other by one predetermined time period.

A semiconductor integrated circuit that performs decoding processing on blocks of a compressed video, the decoding processing including motion compensation processing, the semiconductor integrated circuit comprising:

• a memory that stores reference pictures;
• a compensation circuit unit (i) that includes an input buffer for storing one or more of the reference pictures, the input buffer having a capacity that sufficiently stores reference pictures corresponding to two blocks, and (ii) that sequentially performs the motion compensation processing block by block with reference to the reference pictures stored in the input buffer;
• and
• a reference picture transfer circuit unit that sequentially transfers reference pictures corresponding to two adjacent blocks from the memory to the input buffer included in the compensation circuit unit such that (i) reference pictures corresponding to a first block from among the two adjacent blocks are transferred during a first two consecutive predetermined time periods and (ii) reference pictures corresponding to a second block from among the two adjacent blocks are transferred during a second two consecutive predetermined time periods,
• wherein the first two consecutive predetermined time periods and the second two consecutive predetermined time periods overlap each other by one predetermined time period.