US 8,427,952 B1Granted

Microcode engine for packet processing

AssigneePacket Plus, Inc.

InventorJonathan R. Pearce

Life of this patent

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Abstract

Apparatus and methods to efficiently process packet data are disclosed. In one embodiment, a microcode engine designed to efficiently parse packet data may use instructions that are tailored to parse packet data fields of a data packet having nested protocols. The microcode engine design and the instruction set may enable highly efficient packet processing while preserving flexibility as to the packet protocols that can be processed. The implementation can be both specific to a packet processing task while allowing reprogramming to perform a different specific task simply by changing the instructions. The microcode engine may execute instructions in a single clock cycle or in a pipelined configuration to generate appropriately modified packet data. The microcode engine may operate in lock step with received packet data.

Claims26

Dependent claims

A microcode engine for processing packet data, the microcode engine comprising:

a program memory comprising a plurality of instructions for processing a stream of received packet data, wherein each instruction includes a plurality of instruction fields;
a plurality of execution hardware blocks responsive to the instructions to perform respective functions on the received packet data, each of the plurality of hardware blocks corresponding to a respective instruction field, wherein the plurality of execution hardware blocks comprise:
comparison circuitry to perform a masked comparison of the received packet data;
and
branched decision circuitry to determine when to branch from a sequential reading of instructions from the program memory;
instruction decode circuitry to read a current instruction from the program memory, to provide instruction fields of the current instruction to the corresponding execution hardware blocks for execution, to read, based on an output of the branched decision circuitry, a next instruction from the program memory, and to provide instruction fields of the next instruction to the corresponding execution hardware blocks for execution;
a data stream receiver to directly receive a stream of data packets for processing, the stream of data packets comprising the received packet data, the data stream receiver providing the received packet data to the execution hardware blocks, synchronously with the provision of the instruction fields, based on an instruction of the plurality of instructions;
and
execution control circuitry to direct reads from the data stream receiver for applying one or more of the instructions stored in the program memory to a current data word of the received packet data, and to stall reads from the data stream receiver so as to apply both the current instruction and the next instruction to the current data word.

6 more elements

A method for processing packet data on a network device having a plurality of execution hardware blocks, the method comprising:

receiving, directly via a data stream receiver, packet data;
reading a current instruction from a program memory, the current instruction having a plurality of instruction fields corresponding to the plurality of execution hardware blocks, the program memory having a plurality of instructions to process the received packet data;
synchronously communicating to the execution hardware blocks both a current data word of the received packet data and the corresponding instruction fields of the current instruction for execution by the respective execution hardware blocks;
performing respective functions of the execution hardware blocks on the current data word according to the corresponding instruction fields of the current instruction;
performing a masked comparison of the received packet data;
determining when to branch from a sequential reading of instructions from the program memory;
reading, based on the determination, a next instruction from the program memory;
providing instruction fields of the next instruction to the corresponding execution hardware blocks for execution;
and
stalling reads from the data stream receiver so as to apply both the current instruction and the next instruction to the current data word.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/730,676Filed 24 Mar 2010 · us provisional application
Priority: 24 Mar 2009
Granted: 23 Apr 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 9/3893
Using a plurality of independent parallel functional units: controlled in tandem, e.g. multiplier-accumulator
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/3889
Using a plurality of independent parallel functional units: controlled by multiple instructions, e.g. MIMD, decoupled access or execute
G06F
Computing and data processing