Memory with output control
AssigneeMosaid Technologies Incorporated
InventorsHakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
Life of this patent
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Abstract
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
Claims19
A memory device comprising:
- flash memory;
- a clock input configured to receive a clock signal;
- a common command and data input configured to receive input data and command data at different times;
- a first control input configured to receive a first of two control signals;
- a second control input configured to receive a second of the two control signals;
- core circuitry configured to execute an operation on the flash memory corresponding to the command data;
- and
- latch circuitry configured to:
- latch the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common command and data input, and
- latch the input data in synchronization with both rising and falling edges of the clock signal.
A method carried out in a memory device having flash memory and a common command and data input, the method comprising:
- receiving a clock signal;
- receiving, at the common command and data input and at different times, input data and command data;
- receiving a first of two control signals;
- receiving a second of the two control signals;
- latching the command data while the first of the two control signals is held at an active logic level for at least a duration of time that the command data is received at the common command and data input;
- latching the input data in synchronization with both rising and falling edges of the clock signal;
- and
- executing an operation on the flash memory corresponding to the command data.
Dependencies are inferred from the claim text.