Implementing single bit redundancy for dynamic SRAM circuit with any bit decode

A dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode comprising:

• a series of merged bit column select and redundancy steering multiplexers;
• each of said merged bit column select and redundancy steering multiplexers having a plurality of inputs and one output;
• each of a plurality of bitline columns and a pair of redundancy columns connected to a respective input of said series of said merged bit column select and redundancy steering multiplexers with an adjacent pair of bitline columns connected to a respective adjacent pair of inputs of a next adjacent one of said series of merged bit column select and redundancy steering multiplexers;
• a respective select signal input applied to control each said merged bit column select and redundancy steering multiplexer;
• and
• select signal generation logic receiving a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.

A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:

• a dynamic Static Random Access Memory (SRAM) circuit tangibly embodied in the machine readable medium used in the design process, said dynamic SRAM circuit for implementing single bit redundancy with any bit decode, said dynamic SRAM circuit comprising:
• a series of merged bit column select and redundancy steering multiplexers;
• each of said merged bit column select and redundancy steering multiplexers having a plurality of inputs and one output;
• each of a plurality of bitline columns and a pair of redundancy columns connected to a respective input of said series of said merged bit column select and redundancy steering multiplexers with an adjacent pair of bitline columns connected to a respective adjacent pair of inputs of a next adjacent one of said series of merged bit column select and redundancy steering multiplexers;
• a respective select signal input applied to control each said merged bit column select and redundancy steering multiplexer;
• and
• select signal generation logic receiving a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said dynamic SRAM circuit.