US 8,427,892 B2Granted

Write strobe generation for a memory interface controller

AssigneeJuniper Networks, Inc.

InventorsSrinivas Venkataraman, Praveen Garapally

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Abstract

A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.

Claims17

Dependent claims

A device comprising:

a memory to store data;
and a memory controller connected to the memory via a plurality of data lines and a strobe line, the memory controller using the plurality of data lines to write a data burst as a plurality of data signals, the memory controller using the strobe line to transmit a strobe signal, the strobe signal being used to control writing of the data signals to the memory, and the memory controller including:
a plurality of write data generation circuits that each transmit one of the plurality of data signals on one of the plurality of data lines, the plurality of write data generation circuits being controlled by write enable signals, and a write strobe generation circuit to generate the strobe signal and the write enable signals, the write strobe generation circuit including:
a first flip-flop and a second flip-flop, a logic OR gate connected to receive an output of the first flip-flop and an output of the second flip-flop, a third flip-flop connected to receive an output of the logic OR gate, a first logic NAND gate connected to receive the output of the logic OR gate and a clock signal, a second logic NAND gate connected to receive the output of the first flip-flop and an inverted output of the second flip-flop, a fourth flip-flop connected to receive an output of the second logic NAND gate, and a third logic NAND gate connected to receive an output of the first logic NAND gate and an output of the fourth flip-flop, logic to generate a first signal that defines portions of the strobe signal, the logic to generate the first signal including:
a first pair of serially connected flip-flops that receive the output of the third flip-flop, the first pair of serially connected flip-flops being clocked by a clock that has a frequency that is twice a write frequency for the memory, and a delay chain to:
receive an output of the first pair of serially connected flip-flops, and output the first signal based on the received output of the first pair of serially connected flip-flops, a buffer to receive the first signal, and logic to generate, based on an output of the third logic NAND gate, a second signal that is an input to the buffer.

3 more elements

A non-transitory computer readable memory to store instructions, the instructions comprising:

one or more instructions that, when executed by a device, cause the device to transmit, to a memory device, data signals from a plurality of write data generation circuits, the plurality of write data generation circuits being controlled by a write enable signal;
one or more instructions that, when executed by the device, cause the device to transmit the write enable signal to the plurality of write data generation circuits;
and one or more instructions that, when executed by the device, cause the device to transmit a strobe signal to the memory device, the strobe signal being used to signal a beginning of a write data burst and an end of the write data burst, the one or more instructions to transmit the write enable signal further including:
one or more instructions that, when executed by the device, cause the device to generate a first signal used to generate the write enable signal, one or more instructions that, when executed by the device, cause the device to generate a second signal, and one or more instructions that, when executed by the device, cause the device to generate the write enable signal based on the first signal, the one or more instructions to generate the first signal further including:
one or more instructions that, when executed by the device, cause the device to clock, at a frequency that is twice a write frequency for the memory device, a first pair of serially connected flip-flops, and one or more instructions that, when executed by the device, cause the device to delay, based on an output of the first pair of serially connected flip-flops, output of the first signal, the one or more instructions to generate the second signal, further including:
one or more instructions that, when executed by, the device cause the device to clock, at the frequency that is twice the write frequency for the memory device, a second pair of serially connected flip-flops, and one or more instructions that, when executed by the device, cause the device to delay, based on an output of the second pair of serially connected flip-flops, output of the second signal.

3 more elements

A method comprising:

providing, by a plurality of write data generation circuits in a network device, data signals to a memory device, each of the plurality of write data generation circuits being controlled by a write enable signal;
generating, by the network device, a strobe signal;
generating, by the network device, the write enable signal, the generating of the write enable signal further including:
generating a first signal to initiate generation of the write enable signal, the generating of the first signal including:
clocking, at a frequency that is twice a write frequency for the memory device, a first pair of serially connected flip-flops, delaying, based on an output of the first pair of serially connected flip-flops, an output of the first signal, generating a second signal that defines portions of the strobe signal, the generating of the second signal further including:
clocking, at the frequency that is twice the write frequency for the memory device, a second pair of serially connected flip-flops, and delaying, based on an output of the second pair of serially connected flip-flops, an output of the second signal, and generating, based on the first signal, the write enable signal for the plurality of write data generation circuits;
and transmitting, by the network device, the strobe signal to the memory device and the write enable signal to the plurality of write data generation circuits.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/156,134Filed 8 Jun 2011 · continuation
Priority: 23 Jun 2009
Published: US 2011/0235446 A129 Sep 2011
Granted: 23 Apr 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 13/1689
Details of memory controller: synchronisation and timing concerns
Y02D 10/00
Energy efficient computing
G06F
Computing and data processing
Y02D
Climate change mitigation technologies in information and communication technologies [ict], i.e. information