Memory device and associated main word line and word line driving circuit
AssigneeElite Semiconductor Memory Technology Inc.
InventorMin Chung Chou
Life of this patent
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Abstract
A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected.
Claims4
A main word line driving circuit for driving word lines in a memory device, comprising:
- a first level shifting unit configured to convert a decode signal into a first operative signal, wherein the first level shifting unit comprising:
- a latching unit;
- a first NMOS transistor having a gate connected to a second bias voltage, a source connected for receiving the decode signal, and a drain connected to the latching unit;
- and
- a second NMOS transistor having a gate connected for receiving the decode signal, a source connected to a third bias voltage, and a drain connected to the latching unit;
- a second level shifting unit configured to convert the decode signal into a second operative signal;
- and
- an inverting unit configured to receive the first and second operative signals for driving the word lines;
- wherein a supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the word lines in the memory device are selected or partially selected and switched to the second bias voltage regardless of a first word line activation signal and a second word line activation signal when the word lines in the memory device are deselected.
A word line driving circuit for driving word lines in a memory device, comprising:
- a sub-word line driving circuit configured to convert an output signal of a main word line driving circuit into a driving signal for the word line in response to first and second activation signals;
- and
- the main word line driving circuit, comprising:
- a first level shifting unit configured to convert a decode signal into a first operative signal, wherein the first level shifting unit comprising:
- a latching unit;
- a first NMOS transistor having a gate connected to a second bias voltage, a source connected for receiving the decode signal, and a drain connected to the latching unit;
- and
- a second NMOS transistor having a gate connected for receiving the decode signal, a source connected to a third bias voltage, and a drain connected to the latching unit;
- a second level shifting unit configured to convert the decode signal into a second operative signal;
- and
- an inverting unit configured to receive the first and second operative signals and then generating the output signal to the sub-word line driving circuit;
- wherein a supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the word lines in the memory device are selected or partially selected and switched to the second bias voltage regardless of a first word line activation signal and a second word line activation signal when the word lines in the memory device are deselected.
Dependencies are inferred from the claim text.