Word-line driver using level shifter at local control circuit

A circuit device, comprising:

• a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal;
• and
• a two-gate delay word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array,
• wherein the two-gate delay word-line driver reduces gate delay from the level shifter and includes a first gate having a first transistor to receive the level shifted first address signal from the level shifter and a second transistor to receive the first address signal, wherein the first gate outputs a low signal responsive to receiving a high signal from the first address signal.

A memory circuit comprising:

• a local control circuit having a level shifter for shifting a first address signal received from a main control circuit from a first voltage level to a second voltage level to provide a level shifted first address signal;
• a word-line driver configured to receive the level shifted address signal from the level shifter and a plurality of address signals from the main control circuit;
• and
• a memory cell array having a word line that is coupled to an output of the word-line driver,
• wherein the world-line driver is a two-gate delay word-line driver comprising a first gate having a first transistor for receiving the level shifted first address signal from the level shifter and a second transistor for receiving the first address signal, which reduces gate delay from the level shifter,
• wherein the second transistor is provided between a power supply terminal and an output of the first gate and is coupled in series with the first transistor, and
• wherein the first gate includes the second transistor that, when outputting a low signal responsive to receiving a high signal from the first address signal, turns off prior to the first transistor to reduce the gate delay from the level shifter.

A memory circuit, comprising:

• a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal;
• a four-gate delay word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input to receive the level shifted address signal from the level shifter;
• and
• a memory cell array having a word line that is coupled to an output of the word-line driver, wherein the four-gate delay word-line driver includes a decoder stage that includes a first gate and second gate to receive second and third address signals of the plurality of address signals,
• wherein the four-gate delay word-line driver reduces gate delay from the level shifter and includes a third gate having a first transistor to receive the first address signal from the level shifter and a first inverter to receive the first address signal, wherein the third gate outputs a low signal responsive to receiving a high signal from the first address signal.