Memory device with trimmable power gating capabilities

An electronic system, comprising:

• at least one integrated circuit, the at least one integrated circuit including at least one power gating circuit for use with a memory device having at least one memory cell including a storage element electrically connected with a source potential line, the at least one power gating circuit comprising:
• a clamp circuit electrically connected between the source potential line and a voltage source of the memory device, the clamp circuit being operative to regulate a voltage level on the source potential line relative to the voltage source;
• and
• a control circuit connected with the source potential line, the control circuit being operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device, a coarseness by which the voltage level on the source potential line is adjusted being selectively controlled by the control circuit as a function of at least a first control signal.

An integrated circuit comprising at least one memory device, the at least one memory device comprising:

• at least one memory cell including a storage element electrically connected with a source potential line, a drive strength of the storage element being controlled as a function of a voltage level on the source potential line;
• a clamp circuit electrically connected between the source potential line and a voltage source, the clamp circuit being operative to regulate the voltage level on the source potential line relative to the voltage source;
• and
• a control circuit connected with the source potential line, the control circuit being operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device, a coarseness by which the voltage level on the source potential line is adjusted being selectively controlled by the control circuit as a function of at least a first control signal.