Operating memory cells
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
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Abstract
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells are coupled between the edge cells. The method includes programming a non-edge cell within a first threshold voltage (Vt) distribution. The method also includes programming an edge cell within a second Vt distribution, wherein the first and second Vt distributions correspond to a same one of a number of data states, and wherein the second Vt distribution is different than the first Vt distribution for at least one of the number of data states.
Claims25
A method for operating an array of memory cells, comprising:
- programming a first cell within a first threshold voltage (Vt) distribution to indicate a data state;
- and
- programming a second cell within a second Vt distribution to indicate the data state, wherein the second cell is closer to a select gate transistor than the first cell, wherein the first and the second Vt distributions correspond to the data state, and wherein the second Vt distribution is different than the first Vt distribution.
A method for operating an array of memory cells, comprising:
- sensing a first memory cell with a first sensing voltage that corresponds to a data state;
- sensing a second memory cell with a second sensing voltage that corresponds to the data state, wherein the second memory cell is closer to a select gate transistor than the first memory cell, wherein the first and the second sensing voltages correspond to the data state, and wherein the second sensing voltage is different than the first sensing voltage.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array of memory cells and configured to:
- sense a first cell with a first sensing voltage corresponding to a data state;
- and
- sense a second cell with a second sensing voltage corresponding to the data state, wherein the second cell is closer to a select gate transistor than the first cell and wherein the second sensing voltage is different than the first sensing voltage.
A memory device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array of memory cells and configured to:
- apply programming pulses to a first cell such that the first cell stores a charge within a first threshold voltage (Vt) distribution to indicate a data state;
- and
- apply programming pulses to a second cell such that the second cell stores a charge within a second Vt distribution to indicate the data state, wherein the second cell is closer to a select gate transistor than the first cell, wherein the first and the second Vt distributions correspond to the data state, and wherein the second Vt distribution is different than the first Vt distribution.
A memory device, comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array and configured to:
- program a first cell to one of a number of states;
- program a second cell to the one of the number of states, wherein the second cell is closer to a select gate transistor than the first cell;
- sense the first cell with a first sensing voltage that corresponds to the one of the number of data states;
- and
- sense the second cell with a second sensing voltage that corresponds to the one of the number of data states, wherein the first and the second sensing voltages are used to sense the one of the number of states, and wherein the first sensing voltage is different than the second sensing voltage.
Dependencies are inferred from the claim text.