US 8,427,876 B2Granted

Semiconductor storage device and control method thereof

AssigneeKabushiki Kaisha Toshiba

InventorHideto Takekida

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Abstract

In one embodiment, there is provided a semiconductor storage device including: a memory cell array; a high voltage generator; and a controller that controls the high voltage generator. When a word line to is selected from word lines, the controller controls the high voltage generator to: apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line; apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage; and apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word line and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.

Claims6

Dependent claims

A semiconductor storage device comprising:

a memory cell array comprising:
a source line arranged in a row direction;
a plurality of bit lines arranged in a column direction perpendicular to the row direction;
a plurality of cell units arranged in the column direction, each of the cell units comprising:
a memory cell group comprising a plurality of nonvolatile memory cells connected in series in the row direction;
a first selection gate transistor connected to one end of the memory cell group such that the memory cell group is connected to a corresponding one of the bit lines;
and
a second selection gate transistor connected to the other end of the memory cell group such that the memory cell group is connected to the source line;
a plurality of word lines arranged in the row direction, wherein control gates of the memory cells of the plurality of cell units, which are arranged in the same line, are connected through a corresponding one of the word lines;
a selection gate line, wherein gates of the first or second selection gate transistors of the cell units are connected through the selection gate line;
a high voltage generator that generate a high voltage from a supply voltage supplied from outside and provides the high voltage to the respective word lines;
and
a controller that controls the high voltage generator,
wherein when a word line to which a data read voltage is to be applied is selected from the plurality of word lines, the controller controls the high voltage generator to:
apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line;
apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage;
and
apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word lines and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.

15 more elements

A control method for a semiconductor storage device, the semiconductor storage device comprising:

a memory cell array comprising:
a source line arranged in a row direction;
a plurality of bit lines arranged in a column direction perpendicular to the row direction;
a plurality of cell units arranged in the column direction, each of the cell units comprising:
a memory cell group comprising a plurality of nonvolatile memory cells connected in series in the row direction;
a first selection gate transistor connected to one end of the memory cell group such that the memory cell group is connected to a corresponding one of the bit lines;
and a second selection gate transistor connected to the other end of the memory cell group such that the memory cell group is connected to the source line;
a plurality of word lines arranged in the row direction, wherein control gates of the memory cells of the plurality of cell units, which are arranged in the same line, are connected through a corresponding one of the word lines;
a selection gate line, wherein gates of the first or second selection gate transistors of the cell units are connected through the selection gate line;
a high voltage generator that generate a high voltage from a supply voltage supplied from outside and provides the high voltage to the respective word lines;
and a controller that controls the high voltage generator, the control method comprising:
when selecting a word line to which a data read voltage is to be applied from the plurality of word lines,
(a) applying a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line;
(b) applying a second read pass voltage to a second adjacent word line adjacent to the first word lines, wherein the second read pass voltage is higher than the first read pass voltage;
and
(c) applying a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word lines and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/188,546Filed 22 Jul 2011
Priority: JP 2010-16648923 Jul 2010
Published: US 2012/0020165 A126 Jan 2012
Granted: 23 Apr 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/3418
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: disturbance prevention or evaluation;…
G11C
Static stores