Nonvolatile memory device and system performing repair operation for defective memory cell

#Embodiments of the inventive concept relate generally to semiconductor memory technology. More particularly, embodiments of the inventive concept relate to nonvolatile memory devices and systems capable of performing repair operations for defective memory cells.

#Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power.

#Examples of volatile memory devices include static random-access memory (SRAM) devices, dynamic random-access memory (DRAM) devices, and synchronous dynamic random-access memory (SDRAM) devices. Examples of nonvolatile memory devices include read-only memory (ROM) devices, programmable read-only memory (PROM) devices, electrically programmable read-only memory (EPROM) devices, electrically erasable and programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random-access memory (PRAM) devices, magnetic random-access memory (MRAM) devices, resistive random-access memory (RRAM) devices, and ferroelectric random-access memory (FRAM) devices. Flash memory devices can be further divided into two categories including NOR-type flash memory devices and NAND-type flash memory devices.

#FIG. 1 is a perspective view of a three-dimensional memory cell array according to an embodiment of the inventive concept.

#FIG. 2 is a cross-sectional view of the three-dimensional memory cell array taken along a line I-I′ of FIG. 1.

#FIG. 3 is a cross-sectional view illustrating a transistor structure of FIG. 2.

#Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

#FIG. 1 is a perspective view of a three-dimensional memory cell array 1000 according to an embodiment of the inventive concept.

#Referring to FIG. 1, three-dimensional memory cell array 1000 comprises a substrate 1111, semiconductor pillars 1113, data storage layers 1116, word lines 1211˜1293, common source lines 1311˜1314, drains 1320, and bit lines 1331˜1333.