Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

An integrated circuit including a non-Flash re-writeable non-volatile memory, comprising:

• a semiconductor substrate;
• a front-end-of-the-line (FEOL) logic layer including active circuitry fabricated on the semiconductor substrate;
• one or more layers of back-end-of-the-line (BEOL) memory in direct contact with and fabricated directly above the semiconductor substrate;
• and
• at least one two-terminal cross-point memory array embedded in each layer of BEOL memory, each two-terminal cross-point memory array including
• a plurality of X-line conductive array lines,
• a plurality of Y-line conductive array lines, the plurality of X-line and Y-line conductive array lines are electrically coupled with at least a portion of the active circuitry, and
• a plurality of discrete re-writeable two-terminal non-volatile memory elements, each memory element disposed between a cross-point of a set of X-line conductive array lines and a set of Y-line conductive array lines and is directly electrically in series with its respective X-line and Y-line conductive array lines, each memory element in the layer of BEOL memory having a structure that is associated with different parameter values than memory elements in other layers of BEOL memory, and
• wherein the active circuitry includes a characteristic adjuster configured to adjust an access signal for each layer in the one or more layers of BEOL memory.