Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion

A magnetic memory array

• comprising:
• a plurality of magnetic memory elements, each of the plurality of magnetic memory elements capable of storing a plurality of magnetic states, each state representative of a logic value, the magnetic memory element including,
• a free layer having at least one lateral surface on top of which are formed at least two stacks, the free layer having an anti-parallel domain and a parallel domain separated by a domain wall, the domain wall having an alterable position, the position of the domain wall defining the state of the magnetic memory element;
• a first stack disposed upon the lateral surface of the free layer;
• a second stack disposed upon the lateral surface of the free layer;
• and
• a magnetic tunneling junction (MTJ) disposed upon the free layer, between the first stack and the second stack, and
• a plurality of access transistors, each of the plurality of access transistors coupled to one of the plurality of magnetic memory elements;
• wherein the position of the domain wall relative to the MTJ defines the magnetic state of the magnetic memory element.