Thermal power plane for integrated circuits

An data processing system, comprising:

• a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer;
• and
• a power delivery layer coupled, via a second set of coupling devices, to the processor layer, wherein:
• the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device,
• the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias (TLVs),
• each TLV in the plurality of TLVs is coupled to one of the plurality of conductors or the one or more ground planes while not being coupled to other ones of the plurality of TLVs, and
• the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

A method, in a data processing system, for a thermal power plane that delivers power to integrated circuits and constitutes a minimal thermal resistance in a three-dimensional very-large-scale integration (VLSI) device, the method comprising:

• coupling a processor layer to at least one signaling and input/output (I/O) layer using a first set of coupling devices;
• and
• coupling a power delivery layer to the processor layer using a second set of coupling devices, wherein:
• the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device,
• the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias (TLVs),
• each TLV in the plurality of TLVs is coupled to one of the plurality of conductors or the one or more ground planes while not being coupled to other ones of the plurality of TLVs, and
• the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.