Thin film transistor substrate including disconnection prevention member

A thin film transistor array panel, comprising:

• a display area comprising:
• a gate line;
• a data line insulated from and crossing the gate line;
• a thin film transistor connected to the gate line and the data line;
• a pixel electrode connected to the thin film transistor;
• and
• a peripheral area disposed on the periphery of the display area and comprising:
• a driving signal line formed from the same layer of material as the gate line and configured to receive an external signal;
• a gate insulating layer disposed on the driving signal line;
• a connection signal line disposed on the gate insulating layer and formed from the same layer of material as the data line;
• a disconnection prevention member overlapping a first side surface of the connection signal line;
• and
• a connection assistance member disposed on the disconnection prevention member and connecting the driving signal line and the connection signal line,
• wherein the first side surface of the connection signal line has a reverse-tapered etching profile.