Array substrate for transflective liquid crystal display device and method of fabricating the same

An array substrate for a transflective liquid crystal display device, comprising:

• a substrate;
• first and second gate lines on the substrate along a first direction;
• a common line parallel to and between the first and second gate lines;
• a gate electrode connected to the first gate line;
• a gate insulating layer on the first and second gate lines, the gate electrode and the common line;
• a data line over the gate insulating layer and along a second direction, the data line crossing the first and second gate lines to define a pixel region, the pixel region divided into a transmissive area and a reflective area by the common line;
• a semiconductor layer on the gate insulating layer over the gate electrode;
• source and drain electrodes over the semiconductor layer and spaced apart each other;
• a first passivation layer over the data line, the source electrode and the drain electrode substantially all over the substrate;
• a reflective layer over the first passivation layer in the reflective area;
• a second passivation layer over the reflective layer and having a flat top surface in the reflective layer;
• a pixel electrode over the first and second passivation layers and connected to the drain electrode through a drain contact hole, the pixel electrode having a plate shape;
• a third passivation layer over the pixel electrode;
• and
• a common electrode over the third passivation layer substantially all over the substrate, the common electrode having first openings and second openings corresponding to the transmissive area and the reflective area, respectively, wherein the first openings are spaced apart from each other and are parallel to the data line, and the second openings are spaced apart from each other and are slant an a predetermined angle with respect to the data line, wherein first ends of the first openings overlap the second gate line, second ends of the first openings overlap the common line, first ends of the second openings overlap the common line, and second ends of the second openings overlap the first gate line.