Validating a graphics pipeline using pre-determined schedules
AssigneeNVIDIA Corporation
InventorsViet-Tam Luu, Russell Pflughaupt
Life of this patent
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Abstract
Determining a schedule of instructions for an integrated circuit graphics pipeline. The method includes accessing a state of a host system. The state comprises operations to be performed on fragments to be processed by the graphics pipeline. The method further includes determining a vector based on the state and indexing a table based on the vector to obtain a predetermined listing and ordering of macro-operations to be executed. The method still further includes determining instructions for programming the graphics pipeline based the executing of the macro-operations in the scheduled order.
Claims39
A method of determining a schedule of instructions for a graphics pipeline, said method comprising:
- accessing a state of a host system;
- determining a vector based on said state, wherein said vector comprises information about said state;
- indexing a table based on said vector to obtain a plurality of macro-operations associated with said state, wherein said plurality of macro-operations are associated with at least one operation to be performed by said graphics pipeline;
- and
- determining at least one instruction for programming said graphics pipeline to implement said state, wherein said at least one instruction is determined based on said plurality of macro-operations and also based on context information, wherein said context information comprises data associated with graphics processing that is used to perform said at least one operation.
A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method of determining a schedule of instructions for a graphics pipeline, said method comprising:
- accessing a state of a host system;
- determining a vector based on said state, wherein said vector comprises information about said state;
- indexing a table based on said vector to obtain a plurality of macro-operations associated with said state, wherein said plurality of macro-operations are associated with at least one operation to be performed by said graphics pipeline;
- and
- determining at least one instruction for programming said graphics pipeline to implement said state, wherein said at least one instruction is determined based on said plurality of macro-operations and also based on context information, wherein said context information comprises data associated with graphics processing that is used to perform said at least one operation.
A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said system implement a method of determining a schedule of instructions for a graphics pipeline, said method comprising:
- accessing a state of a host system;
- determining a vector based on said state, wherein said vector comprises information about said state;
- indexing a table based on said vector to obtain a plurality of macro-operations associated with said state, wherein said plurality of macro-operations are associated with at least one operation to be performed by said graphics pipeline;
- and
- determining at least one instruction for programming said graphics pipeline to implement said state, wherein said at least one instruction is determined based on said plurality of macro-operations and also based on context information, wherein said context information comprises data associated with graphics processing that is used to perform said at least one operation.
Dependencies are inferred from the claim text.