Information processing device, image display device, and information processing method

An information processing method for an information processing device having a first processing unit and a second processing unit accessed by the first processing unit, the second processing unit including a control register accessible by the first processing unit, a data buffer accessible by the first processing unit, a host controller that has a plurality of interface circuits connected with a serial bus, and an arbiter that arbitrates transmission of read data or write data between the control register, the data buffer, and the host controller, the method comprising:

• allowing the first processing unit to assert a first chip select signal or a second chip select signal according to an address space to be accessed;
• allowing the first processing unit to access the second processing unit by an access method corresponding to the chip select signal asserted by the first processing unit:,
• buffering data transmitted via the serial bus connected with respective interface circuits included in the plural interface circuits;
• and
• performing serial/parallel conversion or parallel/serial conversion of the data transmitted via the serial bus connected with the interface circuits included in the plural interface circuits and arbitrated by the arbiter,
• wherein the first processing unit accesses the second processing unit by a first access method when asserting the first chip select signal, and accesses the second processing unit when asserting the second chip select signal.

An information processing device comprising:

• a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access;
• a second processing unit accessible by the first processing unit by a first access method or a second access method;
• and
• a supplementary processing unit that has a decoder for decoding the first chip select signal, the second chip select signal, and the address corresponding to the address space accessed by the first processing unit,
• wherein
• when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method,
• when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method, and
• the supplementary processing unit switches between change timing of an access control signal outputted to the second processing unit by the first access method and change timing of an access control signal outputted to the second processing unit by the second access method based on a decode result from the decoder.

An information processing method for an information processing device having a first processing unit, a second processing unit accessed by the first processing unit, and a supplementary processing unit that has a decoder, comprising:

• allowing the first processing unit to assert a first chip select signal or a second chip select signal according to an address space to be accessed;
• allowing the first processing unit to access the second processing unit by an access method corresponding to the chip select signal asserted by the first processing unit;
• decoding the first chip select signal, the second chip select signal, and the address corresponding to the address space accessed by the first processing unit;
• and
• switching between change timing of an access control signal outputted to the second processing unit by the first access method and change timing of an access control signal outputted to the second processing unit by the second access method based on a decode result from the decoder,
• wherein the first processing unit accesses the second processing unit by a first access method when asserting the first chip select signal, and accesses the second processing unit when asserting the second chip select signal.