Display panel

A display panel, comprising:

• a substrate;
• a pixel array disposed on the substrate;
• a plurality of first shift registers disposed on the substrate for outputting a plurality of first scanning signals sequentially;
• and
• a plurality of second shift registers disposed on the substrate for outputting a plurality of second scanning signals sequentially,
• wherein a jth first shift register stops outputting a jth first scanning signals according to a jth second scanning signal, a jth second shift register stops outputting the jth second scanning signal according to the (j+1)th first scanning signal while j is a positive integer, and the first scanning signals and the second scanning signals are used for driving the pixel array, each of the first shift registers comprises:
• a first transistor, a first terminal of the first transistor being coupled to a control terminal of the first transistor;
• a second transistor, a first terminal of the second transistor being coupled to the first terminal of the first transistor, a second terminal of the second transistor being coupled to a second terminal of the first transistor;
• a third transistor, a first terminal of the third transistor being coupled to the second terminal of the first transistor, a second terminal of the third transistor being coupled to a gate low voltage;
• a fourth transistor, a first terminal of the fourth transistor being coupled to the second terminal of the first transistor, a second terminal of the fourth transistor being coupled to the gate low voltage;
• a fifth transistor, a first terminal of the fifth transistor being coupled to a control terminal of the fourth transistor, a second terminal of the fifth transistor being coupled to the gate low voltage, a control terminal of the fifth transistor being coupled to the second terminal of the first transistor;
• a sixth transistor, a control terminal of the sixth transistor being coupled to the second terminal of the first transistor;
• a seventh transistor, a first terminal of the seventh transistor being coupled to a second terminal of the sixth transistor, a second terminal of the seventh transistor being coupled to the gate low voltage, a control terminal of the seventh transistor being coupled to the control terminal of the fourth transistor;
• an eighth transistor, a first terminal of the eighth transistor being coupled to the second terminal of the sixth transistor, a second terminal of the eighth transistor being coupled to the gate low voltage;
• a ninth transistor, a first terminal of the ninth transistor being coupled to the second terminal of the sixth transistor, a second terminal of the ninth transistor being coupled to the gate low voltage;
• a first capacitor, coupled between a first terminal of the sixth transistor and the first terminal of the fifth transistor;
• and
• a second capacitor, coupled between the second terminal of the sixth transistor and the control terminal of the sixth transistor,
• wherein, in a 1st first shift register, the first terminal of the first transistor receives a start signal, the control terminal of the second transistor and the control terminal of the eighth transistor receive a reverse signal of a first clocking signal, a control terminal of the third transistor and a control terminal of the ninth transistor receive a 1st second scanning signal, the first terminal of the sixth transistor receives the first clocking signal, the second terminal of the sixth transistor outputs a 1st first scanning signal;
• wherein, in a 2jth first shift register, the first terminal of the first transistor receives a (2j−1)th second scanning signal, the control terminal of the second transistor and the control terminal of the eighth transistor receive the first clocking signal, the control terminal of the third transistor and the control terminal of the ninth transistor receive a 2jth second scanning signal, the first terminal of the sixth transistor receives the reverse signal of the first clocking signal, the second terminal of the sixth transistor outputs a 2jth first scanning signal;
• wherein, in a (2j+1)th first shift register, the first terminal of the first transistor receives a 2jth second scanning signal, the control terminal of the second transistor and the control terminal of the eighth transistor receive the reverse signal of the first clocking signal, the control terminal of the third transistor and the control terminal of the ninth transistor receive a (2j+1)th second scanning signal, the first terminal of the sixth transistor receives the first clocking signal, the second terminal of the sixth transistor outputs a (2j+1)th first scanning signal.