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US 8,427,355 B2Granted
Time-interleaved pipelined-SAR analog to digital converter with low power consumption
AssigneeUniversity of Macau
InventorsSai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
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Abstract
An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
Claims5
An analog-to-digital converter (ADC) circuit, comprising:
- multiple time-interleaved successive approximation register (SAR) ADCs, each of the multiple time-interleaved SAR ADCs comprising:
- a first stage SAR sub-ADC for coarse conversion, the first stage SAR sub-ADC receiving and converting an analog input signal to generate a first digital code and a residue signal;
- a residue amplifier for amplifying the residue signal generated by the first stage SAR sub-ADC to output a amplified residue signal, wherein the residue amplifier is shared between the multiple time-interleaved SAR ADCs;
- a second stage SAR sub-ADC for fine conversion, the second stage SAR sub-ADC receiving and converting the amplified residue signal to generate a second digital code;
- and
- a digital error correction logic for receiving and combining the first digital code generated by the first stage SAR sub-ADC and the second digital code generated by the second stage SAR sub-ADC to generate digital representation of the analog input signal;
- wherein the residue amplifier is a single-stage operation amplifier having a low gain and operating in sub-threshold.
4 more elements
Dependencies are inferred from the claim text.