US 8,427,351 B2 · Digital-to-analog conversion device

Abstract

A digital-to-analog conversion device is disclosed. The digital-to-analog conversion device comprises a variable delay buffer circuit and a plurality of synchronization circuits. The buffer circuit receives a digital signal with a plurality of bits and sequentially outputs a plurality of first complementary digital signal sets delayed according to the order of from MSB to LSB. Each synchronization circuit receives the first complementary digital signal set and a clock signal, uses the clock signal as the timing reference of the first complementary digital signal set, and outputs a second complementary digital signal set corresponding to the first complementary digital signal set to a digital-to-analog conversion unit, so as to convert the second complementary digital signal sets into an analog signal. The present invention uses the delays respectively corresponding to different input bits to control the timing of current switches, whereby the transient glitches are reduced.

Claims11

Dependent claims

A digital-to-analog conversion device comprising:

a variable delay buffer circuit receiving a digital signal to be converted containing a plurality of bits ordered from MSB (Most Significant Bit) to LSB (Least Significant Bit), said variable delay buffer circuit outputting for each bit a first complementary digital signal set, said first complementary digital signal sets for the bits being delayed one with respect to the other according to the order thereof between the MSB and LSB;
a plurality of synchronization circuits respectively receiving said first complementary digital signal sets and a clock signal, using said clock signal as a timing reference of said first complementary digital signal sets, and outputting a plurality of variably delayed second complementary digital signal sets corresponding to said first complementary digital signal sets;
and
a digital-to-analog conversion unit receiving said second complementary digital signal sets and converting said second complementary digital sets into an analog signal.

1 more element

A digital-to-analog conversion device comprising:

a variable delay buffer circuit receiving a digital signal containing a plurality of bits and outputs a plurality of first complementary digital signal sets respectively delayed according to the order from MSB (Most Significant Bit) to LSB (Least Significant Bit);
a plurality of synchronization circuits respectively receiving said first complementary digital signal sets and a clock signal, using said clock signal as a timing reference of said first complementary digital signal sets, and outputting second complementary digital signal sets corresponding to said first complementary digital signal sets;
and
a digital-to-analog conversion unit receiving said second complementary digital signal sets and converting said second complementary digital sets into an analog signal;
wherein each said synchronization circuit is connected with a low-amplitude switch driver set that is connected with a high voltage, receives one said second complementary digital set, regulates an amplitude of said second complementary digital set to be smaller than an amplitude of a full swing and then outputs said second complementary digital set to said digital-to-analog conversion unit.

2 more elements

Dependencies are inferred from the claim text.

Digital-to-analog conversion device

Life of this patent

Digital-to-analog conversion device

Life of this patent

Abstract

Claims11