Device for controlling a power transistor
AssigneeSchneider Toshiba Inverter Europe SAS
InventorPetar Grbovic
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Abstract
The invention relates to a gate control device for a JFET-type transistor that has a gate, a drain and a source. The gate control device includes a voltage generation circuit comprising an output connected to the gate of the transistor, where the circuit is designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp. A voltage limiting circuit is designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage at the terminals of the JFET transistor has reached said maximum value.
Claims11
A gate control device for a JFET transistor including a gate, a drain and a source, said gate control device comprising:
- a voltage generation circuit including an output connected to the gate of the JFET transistor, said circuit being designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp;
- and
- a voltage limiting circuit connected to the gate and source of the JFET transistor and designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage between the gate and source of the JFET transistor has reached said maximum value, the voltage limiting circuit determining when the gate-source voltage of the JFET transistor reaches the maximum value by directly sensing a gate voltage of the JFET transistor.
A gate control device for a JFET transistor including a gate, a drain and a source, said gate control device comprising:
- a voltage generation circuit including an output connected to the gate of the JFET transistor, said circuit being designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp;
- a voltage limiting circuit designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage between the gate and source of the JFET transistor has reached said maximum value;
- a diode and a capacitor connected in series between a first input of the limiting circuit and ground;
- and
- a stabilization diode connected in parallel with the capacitor.
A power converter with an inverter stage comprising plural JFET transistors, each JFET transistor being controlled by a control device comprising:
- a voltage generation circuit including an output connected to the gate of the JFET transistor, said circuit being designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp;
- and
- a voltage limiting circuit designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage between the gate and source of the JFET transistor has reached said maximum value, the voltage limiting circuit determining when the gate-source voltage of the JFET transistor has reached the predetermined maximum by directly sensing a gate voltage of the JFET transistor.
Dependencies are inferred from the claim text.