Voltage level translator circuit for reducing jitter

A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:

• an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node;
• a load circuit coupled with the input stage, the load circuit being operative to at least temporarily store a signal on at least one of the first and second nodes which is indicative of a logical state of the input signal;
• at least a first output stage connected with the load circuit at the second node and being operative to generate an output signal of the voltage level translator circuit which is indicative of a logical state of the input signal;
• and
• a compensation circuit connected with the first output stage and being operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node;
• wherein the input stage is a differential input stage operative to receive the input signal and a logical complement of the input signal, the input stage comprising first and second NMOS transistors, first source/drains of the first and second NMOS transistors being adapted for connection to a voltage return of the voltage level translator circuit, a gate of the first NMOS transistor being adapted to receive the input signal, a gate of the second NMOS transistor being adapted to receive the logical complement of the input signal, a second source/drain of the first NMOS transistor being connected with the load circuit at the first node, and a second source/drain of the second NMOS transistor being connected with the load circuit at the second node, and wherein the first and second NMOS transistors are low-voltage transistors, and wherein the input stage further comprises first and second low-voltage PMOS transistors, first source/drains of the first and second PMOS transistors being adapted for connection with the first voltage supply, a gate of the first PMOS transistor being adapted to receive the input signal, a gate of the second PMOS transistor being adapted to receive the logical complement of the input signal, a second source/drain of the first PMOS transistor being connected with the second source/drain of the first NMOS transistor, and a second source/drain of the second PMOS transistor being connected with the second source/drain of the second NMOS transistor.

An integrated circuit comprising at least one voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the at least one voltage level translator circuit comprising:

• an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node;
• a load circuit coupled with the input stage, the load circuit being operative to at least temporarily store a signal on at least one of the first and second nodes which is indicative of a logical state of the input signal;
• at least a first output stage connected with the load circuit at the second node and being operative to generate an output signal of the at least one voltage level translator circuit which is indicative of a logical state of the input signal;
• and
• a compensation circuit connected with the first output stage and being operative to balance pull-up and pull-down propagation delays in the at least one voltage level translator circuit as a function of a voltage at the first node;
• wherein the compensation circuit comprises a first PMOS transistor having a first source/drain connected with a first output of the voltage level translator circuit, a second source/drain adapted for connection with the voltage return of the voltage level translator circuit, and a gate connected with the first node of the load circuit.

An electronic system, comprising:

• at least one integrated circuit, the at least one integrated circuit including at least one voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the at least one voltage level translator circuit comprising:
• an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node;
• a load circuit coupled with the input stage, the load circuit being operative to at least temporarily store a signal on at least one of the first and second nodes which is indicative of a logical state of the input signal;
• at least a first output stage connected with the load circuit at the second node and being operative to generate an output signal of the at least one voltage level translator circuit which is indicative of a logical state of the input signal;
• and
• a compensation circuit connected with the first output stage and being operative to balance pull-up and pull-down propagation delays in the at least one voltage level translator circuit as a function of a voltage at the first node;
• wherein the compensation circuit comprises a first PMOS transistor having a first source/drain connected with a first output of the voltage level translator circuit, a second source/drain adapted for connection with the voltage return of the voltage level translator circuit, and a gate connected with the first node of the load circuit.