Ser tolerant flip flop having a redundant latch
AssigneeMarvell International Ltd.
InventorsVinay Chitturi, Oscar M. Siguenza
Life of this patent
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Abstract
A circuit configured to resist a radiation strike includes a latch having an input node and an output node, and a first resistive element configured to be coupled to the first input node to resist a change of a state data at the input node from a radiation strike. The circuit further includes an input stage coupled to the input node and configured to be clocked to transfer the state data to the latch. The circuit further includes a pass circuit configured to be clocked after the input stage to couple the first resistive element to the input node after the input stage transfers the state data to the latch.
Claims23
A circuit comprising:
- a latch having an input node and an output node;
- a resistive element configured to be coupled to the input node to resist a change of state data at the input node from a radiation strike;
- a capacitive element configured to be coupled to the input node to resist a change of the state data at the input node from the radiation strike, the capacitive element including a pair of transistors having coupled gates, a first source-drain region of the pair of transistors coupled to a voltage source and a second source-drain region of the pair of transistors coupled to a ground;
- an input stage coupled to the input node and configured to be clocked to transfer the state data to the latch;
- and
- a pass circuit configured to be clocked after the input stage to couple the resistive element and the capacitive element to the input node after the input stage transfers the state data to the latch.
A circuit comprising:
- a latch having an input node and an output node;
- a first resistive element configured to be coupled to the input node to resist a change of first state data at the input node from a radiation strike;
- an input stage coupled to the input node and configured to be clocked to transfer the first state data to the latch;
- a first pass circuit configured to be clocked after the input stage to couple the first resistive element to the input node after the input stage transfers the first state data to the latch;
- a second resistive element and a capacitive element, each of which is configured to be coupled to the output node to resist a change of second state data at the output node from the radiation strike, the capacitive element including a pair of transistors having coupled gates, a first source-drain region coupled to a voltage source, and a second source-drain region coupled to a ground;
- and
- a second pass circuit configured to be clocked after the input stage to couple the second resistive element and the capacitive element to the output node after the input stage transfers the first state data to the latch.
Dependencies are inferred from the claim text.