Robust time borrowing pulse latches

Circuitry on an integrated circuit, comprising:

• a pulse latch formed from a level sensitive latch that receives at least one clock pulse of a given width;
• and
• pulse generation circuitry that generates the at least one clock pulse, wherein the pulse generation circuitry includes an input that receives a clock signal, an output at which the clock pulse is provided, and logic circuitry with which signals from the output are fed back and combined with the clock signal, wherein the logic circuitry includes a feedback path and at least one NAND gate in the feedback path and wherein the pulse generation circuitry includes a configurable delay element.

Circuitry on an integrated circuit, comprising:

• a pulse latch formed from a level sensitive latch that receives at least one clock pulse of a given width;
• and
• pulse generation circuitry that generates the at least one clock pulse, wherein the pulse generation circuitry includes an input that receives a clock signal, an output at which the clock pulse is provided, and logic circuitry with which signals from the output are fed back and combined with the clock signal, wherein the logic circuitry comprises a feedback path coupled to the output, a delay element, and a configurable multiplexer that selectively includes the delay element in the feedback path.

Circuitry on an integrated circuit, comprising:

• a pulse latch formed from a level sensitive latch that receives at least one clock pulse of a given width;
• and
• pulse generation circuitry that generates the at least one clock pulse, wherein the pulse generation circuitry includes an input that receives a clock signal, an output at which the clock pulse is provided, and logic circuitry with which signals from the output are fed back and combined with the clock signal, wherein the pulse generation circuitry includes a NAND gate that receives the clock signal and the fed back signals from the output, wherein the pulse generation circuitry includes a configurable delay element having at least two delay settings.

Circuitry on an integrated circuit, comprising:

• a pulse latch formed from a level sensitive latch that receives at least one clock pulse of a given pulse width;
• and
• pulse generation circuitry that generates the at least one clock pulse, wherein the pulse generation circuitry includes an input that receives a clock signal, an output at which the clock pulse is provided, and logic circuitry with which signals from the output are fed back and combined with the clock signal, wherein the given pulse width comprises an adjustable pulse width, and wherein the logic circuitry includes at least first and second NAND gates.