Sampling phase lock loop (PLL) with low power clock buffer

A method, comprising:

• receiving an input reference signal at a buffer circuit that includes drain-coupled NMOS and PMOS transistors with an intermediate drain output node;
• generating first and second control signals by:
• inputting the reference signal to the gate of the NMOS transistor;
• inputting the reference signal to an adjustable delay circuit so as to generate a delayed reference signal;
• inputting the delayed reference signal to the gate of the PMOS transistor;
• providing an output from the drain output node as the first control signal;
• and
• inverting the first control signal to provide the second control signal;
• controlling the generation of a PLL output signal by a PLL based on the first control signal;
• controlling the generation of a DLL output signal by a DLL based on the PLL output signal the second control signal;
• and
• controlling the delay of the adjustable delay circuit with the DLL control signal such that the NMOS transistor and the PMOS transistor are not on at the same time.

A system, comprising

• a circuit configured to perform logic operations based on a PLL clock at a specified clock frequency;
• a sampling PLL circuit configured to generate the PLL clock from a reference clock, the sampling PLL circuit operable to phase align the PLL clock with the reference clock;
• and
• an oscillator circuit generating the reference clock;
• the sampling PLL circuit having:
• a sampling phase detector circuit coupled to receive the PLL output clock, and responsive to a sampling control signal to generate a PLL control signal used to phase lock the PLL output clock to the reference clock;
• and
• a buffer circuit receiving the reference clock, and configured to generate the sampling control signal with a substantially square wave duty cycle defined by a sampling edge and a signal edge which establish a sampling duration, the buffer circuit having:
• a first transistor of a first type and a second transistor of a second type coupled in series in a pull-up pull-down arrangement with a buffer output node between the transistors, the transistors characterized by respective threshold voltages;
• a pulser circuit receiving the reference clock and configured to generate a switch control pulse characterized by a switch-on edge and a pulse width;
• the first transistor receiving at its control input the reference clock, and the second transistor receiving at its control input the switch control pulse;
• wherein the pulser circuit is configured to introduce a controlled delay in the switch-on edge of the switch control pulse relative to the reference clock cycling through the threshold voltage of the second transistor, and to control the pulse width of the switch control pulse;
• and
• wherein the buffer circuit is configured such that:
• the first transistor switches on in response to the reference clock cycling through its threshold voltage, thereby transitioning the buffer output node to generate the sampling edge of the sampling control signal;
• the second transistor switches on in response to the switch-on edge of the switch control pulse, thereby transitioning the buffer output node to generate the signal edge of the sampling control signal, and
• the switch-on edge and pulse width of the switch control pulse are controlled such that the first and second transistors are not on at the same time.

A circuit, comprising:

• an oscillator;
• a buffer circuit having
• an adjustable delay circuit coupled to the oscillator;
• an inverting buffer coupled to the adjustable delay circuit and the oscillator;
• and
• an inverter coupled to the output of the inverting buffer;
• a PLL having an input and an output, wherein the input of the PLL is coupled to the output of the inverting buffer;
• and
• a DLL coupled to the output of the PLL and the inverter;
• wherein the DLL is configured to control the adjustable delay circuit.