Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram

A method for performing synchronous logic operations with enhanced security pertaining to a third party attempts in determining aspects of the internal operation or other aspects through monitoring of the current or electromagnetic emissions generated by state changes that occur at clock edge transitions comprising a clock generator with a closed eye diagram;

• wherein said clock generator for producing an output clock with a dosed eye diagram over a plurality of clock cycles is bounded by programmable limits and comprises:
• an input clock signal;
• a random number generator for producing a data word at each output clock transition;
• a first logic module for calculating the time delay from the current output clock transition to the next output clock transition;
• a second logic module for converting the time delay value for the next output clock transition from the first logic module into a value that is relative to the input clock, with ability to extend the time delay value over more than one period of the input clock;
• a delay circuit for producing an output pulse delayed in time to the input clock, wherein the time delay is variable through a control bus;
• a third logic module for producing an output gating signal in the presence of overflow bits from the output of the second logic module;
• an output gating and clock reconstruction circuit.

A method for generating a dock signal with a dosed eye diagram with a minimal reduction in operating frequency in a synchronous logic device, for preventing a third party from determining aspects of the internal operation or data or other aspects through monitoring of the current or electromagnetic emissions generated by state changes that occur at clock edge transitions,

• wherein the said logic device comprises a synchronous logic system without a clock generator and wherein the clock signal is generated by a clock generator,
• wherein the said clock generator for producing an output clock with a closed eye diagram over a plurality of clock cycles is bounded by programmable limits and comprises:
• an input clock signal;
• a random number generator for producing a data word at each output clock transition;
• a first logic module for calculating the time delay from the current output clock transition to the next output clock transition;
• a second logic module for converting the time delay value for the next output clock transition from the first logic module into a value that is relative to the input clock, with ability to extend the time delay value over more than one period of the input clock;
• a delay circuit for producing an output pulse delayed in time to the input clock, wherein the time delay is variable through a control bus;
• a third logic module for producing an output gating signal in the presence of overflow bits from the output of the second logic module;
• an output-gating and clock reconstruction circuit.