Semiconductor package and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJi-hyun Park, Heungkyu Kwon, Min-Ok Na, Taehwan Kim
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Abstract
A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.
Claims29
A semiconductor package comprising:
- a substrate having an insulation layer formed with a first surface roughness in a first region and a second surface roughness in a second region;
- a semiconductor chip;
- and
- a protection layer between the first region and the semiconductor chip,
- wherein top surfaces of the first region and the second region are coplanar.
A semiconductor package, comprising:
- a substrate having connection terminals to connect to a semiconductor chip;
- and
- an insulation layer formed on the substrate to have a first region including a first plurality of grooves and a second region including a second plurality of grooves different from the first plurality of grooves and coplanar with the first region,
- wherein the first region includes a chip mounting area corresponding to the connection terminals, and
- the second region has a surface roughness that is different from a surface roughness of the first region.
Dependencies are inferred from the claim text.