Semiconductor integrated circuit devices having different thickness silicon-germanium layers

A semiconductor integrated circuit device comprising:

• a substrate include gate patterns on a first region and on a second region, wherein spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region;
• source/drain trenches in the substrate on opposite sides of the gate patterns;
• a first silicon-germanium (SiGe) epitaxial layer that partially fills the source/drain trenches, wherein a thickness of the first SiGe epitaxial layer in the source/drain trenches on the second region is larger than a thickness of the first SiGe epitaxial layer in the source/drain trenches on the first region;
• a second SiGe epitaxial layer that is on the first SiGe epitaxial layer, wherein a thickness of the second SiGe epitaxial layer in the source/drain trenches on the first region is larger than a thickness of the second SiGe epitaxial layer in the source/drain trenches on the second region, so that a sum of the thicknesses of the first and second SiGe epitaxial layers is substantially the same in the first and second regions.