A package structure of a semiconductor device integrated with a converter, comprising:
- a lead frame comprising:
- a chip holder, having a first side and a second side disposed oppositely to the first side;
- a first lead, disposed at the first side of the chip holder;
- a second lead, disposed at the first side of the chip holder;
- a third lead, disposed at the first side of the chip holder;
- a forth lead, disposed at the first side of the chip holder, and the third lead and the forth lead being electrically connected to the chip holder;
- a fifth lead, disposed at the second side of the chip holder;
- a sixth lead, disposed at the second side of the chip holder, and the sixth lead-pin being electrically connected to the fifth lead;
- a seventh lead, disposed at the second side of the chip holder;
- and
- an eighth lead, disposed at the second side of the chip holder, and the eighth lead being electrically connected to the seventh lead;
- a semiconductor device disposed on the lead frame comprising:
- a semiconductor substrate, having a first conductive type, wherein a high-side transistor device region and a low-side transistor device region are defined on the semiconductor substrate;
- at least a high-side transistor device, disposed in the high-side transistor device region, the high-side transistor device comprising:
- a doped high-side base region, embedded in the semiconductor substrate of the high-side transistor device region, and the doped high-side base region having a second conductive type;
- a light-doped drain region, embedded in the doped high-side base region, and the light-doped drain region having the first conductive type;
- a doped drain region, disposed within the light-doped drain region, and the doped drain region having the first conductive type;
- a doped high-side source region, embedded in the doped high-side base region at a side of the light-doped drain region, and the doped high-side source region having a first conductive type;
- and
- a high-side gate conductive layer, disposed on the doped high-side base region between the light-doped drain region and the doped high-side source region;
- a high-side drain metal layer, disposed on the semiconductor substrate of the high-side transistor device region, and the high-side drain metal layer being electrically connected to the doped drain region;
- a high-side gate metal layer, disposed on the semiconductor substrate of the high-side transistor device region, and the high-side gate metal layer being electrically connected to the high-side gate conductive layer;
- a common metal layer, disposed under the semiconductor substrate, wherein the common metal layer electrically connects the doped high-side source region and the semiconductor substrate;
- at least a low-side transistor device, disposed in the low-side transistor device region, and the low-side transistor device comprising:
- a gate;
- a doped low-side base region, embedded in the semiconductor substrate of the low-side transistor device region, and the doped low-side base region having a second conductive type;
- and
- a doped low-side source region, embedded in the doped low-side base region, and the doped low-side source region having a first conductive type and serving as a source of the low-side transistor device, wherein the semiconductor substrate serves as a drain of the low-side transistor device;
- a low-side source metal layer, disposed on the semiconductor substrate of the low-side transistor device region, and the low-side source metal layer being electrically connected to the source of the low-side transistor device;
- a low-side gate metal layer, disposed on the semiconductor substrate of the low-side transistor device region, and the low-side gate metal layer being electrically connected to the gate of the low-side transistor;
- and
- a first interlayer dielectric layer, disposed between the semiconductor substrate and the high-side drain metal layer and between the semiconductor substrate and the low-side source metal layer;
- and
- a package, encapsulating the semiconductor device and a portion of the lead frame.