Vertical semiconductor device with thinned substrate
AssigneeIo Semiconductor, Inc.
InventorsStuart B. Molin, Michael A. Stuber
Life of this patent
Estimating the term…
Abstract
A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.
Claims25
An integrated circuit chip comprising:
- a vertical semiconductor device comprising:
- an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least two of the semiconductor structures that are electrically complementary and to enhance thermal dissipation;
- and
- at least one bottom side electrode connected to at least one of the exposed semiconductor structures.
A vertical power device comprising:
- a gate region;
- an active region having first, second and third semiconductor regions, at least a portion of a substrate material below the active region having been removed to isolate the active region and to expose at least two of the first, second and third semiconductor regions that are electrically complementary;
- and
- at least one bottom side electrode connected to at least one of the exposed semiconductor regions;
- and wherein:
- the first semiconductor region is located below the gate region;
- the third semiconductor region isolates the first semiconductor region from the second semiconductor region;
- the third semiconductor region has a bottom boundary and a side boundary;
- the side boundary extends downward from below the gate region to the bottom boundary;
- and
- the first and third semiconductor regions are in contact along the side boundary and are not in contact along the bottom boundary.
Dependencies are inferred from the claim text.