Semiconductor storage device and method of fabricating the same

A semiconductor device comprising:

• at least two memory cells, wherein each of the memory cells contain six transistors, which are two access transistors, two drive transistors, and two load transistors;
• a first poly-silicon wiring layer, a first part of which is a gate of a first access transistor of a first memory cell, and a second part of which is a gate of a first access transistor of a second memory cell;
• a second poly-silicon wiring layer, a first part of which is a gate of a first drive transistor of the first memory cell, a second part of which is a gate of a first load transistor of the first memory cell;
• a third poly-silicon wiring layer, a first part of which is a gate of a second load transistor of the first memory cell and a second part of which is a gate of a second drive transistor of the first memory cell;
• a fourth poly-silicon wiring layer, a first part of which is a gate of a second access transistor of the first memory cell;
• a first P-well region is structured under the first access transistor and the first drive transistor;
• a first N-well region is structured under the first and second load transistors;
• a second P-well region is structured under the second access transistor and the second drive transistor;
• a first ion implantation region is part of the first access transistor and the first drive transistor;
• a second ion implantation region is a part of the first load transistor;
• a third ion implantation region is a part of the second load transistor;
• and
• a fourth ion implantation region is a part of the second access transistor and the second drive transistor, wherein
• all distances between the first poly-silicon wiring layer and the third poly-silicon wiring layer, between the second poly-silicon wiring layer and the fourth poly-silicon wiring layer, and between the second poly-silicon wiring layer of the first memory cell and the second poly-silicon wiring layer of the second memory cell are substantially a same distance,
• all lengths of the first to third poly-silicon wiring layers are substantially a same length,
• the first, second, third, and fourth poly-silicon wiring layers extend in length and width directions wherein the length directions are longer than the width directions,
• the first, second, third, and fourth ion implantation regions extend in length and width directions wherein the length directions are longer than the width directions,
• the length directions of the poly-silicon wiring layers are substantially orthogonal to the length directions of the ion implantation regions,
• the first poly-silicon wiring layer has first and second opposing edges extending in the width direction and the first ion implantation region has first and second opposing edges extending in the length direction, the first poly-silicon wiring layer crosses over the first ion implantation region from the first edge to the second edge of the first ion implantation region, and the second edge of the first poly-silicon wiring layer, which is closer to the first access transistor than the first edge of the first poly-silicon wiring layer, is between the second edge of the first ion implantation region and an interface of the first P-well and the first N-well,
• the second poly-silicon wiring layer has first and second opposing edges extending in the width direction, the second poly-silicon wiring layer crosses over the first ion implantation region from the first edge to the second edge of the first ion implantation region, and the first edge of the second poly-silicon wiring layer, which is closer to the first drive transistor than the second edge of the second poly-silicon wiring layer, is between the first edge of the first ion implantation region and a first P-well of the second memory cell, and crosses over the second ion implantation region from a first edge to a second edge of the second ion implantation region,
• the third ion implantation region has first and second opposing edges extending in the length direction, the third poly-silicon wiring layer crosses over the third ion implantation region from the first edge to the second edge of the third ion implantation region, and the second edge of the second poly-silicon wiring layer is between an extended line of the second edge of the third ion implantation region and an interface between the first N-well and the second P-well,
• the third poly-silicon wiring layer has first and second opposing edges extending in the width direction, and the second ion implantation region has first and second opposing edges extending in the length direction, and the first edge of the third poly-silicon wiring layer, which is closer to the second load transistor than the second edge of the third poly-silicon wiring layer, is between an extended line of the first edge of the second ion implantation region and the interface between the first P-well and the first N-well,
• the fourth ion implantation region has first and second opposing edges extending in the length direction, the third poly-silicon wiring layer crosses over the fourth ion implantation region from the first edge to the second edge of the fourth ion implantation region, the second edge of the third poly-silicon wiring layer is between the second edge of the fourth ion implantation region and a second edge of the second P-well opposing the interface between the first N-well and the second P-well,
• the fourth poly-silicon wiring layer has first and second opposing edges extending in the width direction, the fourth poly-silicon wiring layer crosses over the fourth ion implantation region from the first edge to the second edge of the fourth ion implantation region, and the first edge of the fourth poly-silicon wiring layer, which is closer to the second access transistor than the second edge of the fourth poly-silicon wiring layer, is between the first edge of the fourth ion implantation region and the interface between the first N-well and the second P-well,
• a first edge between the first P-well region and the first N-well region is structured between the first ion implantation region and the second ion implantation region, and a second edge between the first N-well region and the second P-well region is structured between the third ion implantation region and the fourth ion implantation region.