# US 8,421,069 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,421,069 B2 - Document ID: US8421069B2 - Status: Granted - Kind: B2 - Application number: 12/904,579 - Filed: 2010-10-14 - Published: 2011-05-05 - Granted: 2013-04-16 - Earliest claimed: 2009-10-30 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Shunpei Yamazaki; Jun Koyama; Hiroyuki Miyake; Kei Takahashi; Kouhei Toyotaka; Masashi Tsubuku; Kosei Noda; Hideaki Kuwabara - Inventors: Shunpei Yamazaki; Jun Koyama; Hiroyuki Miyake; Kei Takahashi; Kouhei Toyotaka; Masashi Tsubuku; Kosei Noda; Hideaki Kuwabara - Web page: https://patentgrep.com/patent/US8421069B2 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10B 12/05: {Making the transistor} - H10D 1/47: Resistors having no potential barriers - H10D 1/692: {Electrodes} - H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)} - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10D 86/01: Manufacture or treatment - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10D 89/215: {comprising arrangements for charge pumping or biasing substrates} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 90/00: Package configurations - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 44/248: {for antennas} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate; a first gate electrode layer over the semiconductor substrate; a first electrode layer over the semiconductor substrate; a first gate insulating layer over the first gate electrode layer and the first electrode layer; an oxide semiconductor layer over the first gate insulating layer; a first insulating layer over the first electrode layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a second gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a second gate electrode layer over the second gate insulating layer, wherein at least part of the drain electrode layer overlaps with the first electrode layer, and wherein the first insulating layer and the first gate insulating layer are provided between the drain electrode layer and the first electrode layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is a CPU. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is an LSI. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a hydrogen concentration in the oxide semiconductor layer is lower than or equal to 5×1019 atoms/cm3, and wherein a carrier concentration in the oxide semiconductor layer is lower than or equal to 5×1014/cm3. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is an EDMOS circuit. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate electrode is set to a fixed potential or a ground potential. ### Claim 8 A semiconductor device comprising an EDMOS circuit comprising: a semiconductor substrate; a first thin film transistor over the semiconductor substrate; and a second thin film transistor over the semiconductor substrate, wherein the first thin film transistor comprises: a first gate electrode layer; a first gate insulating layer over the first gate electrode layer; an first oxide semiconductor layer over the first gate insulating layer; a first source electrode layer and a first drain electrode layer over the first oxide semiconductor layer; a second gate insulating layer over the first oxide semiconductor layer, the first source electrode layer, and the first drain electrode layer; and a second gate electrode layer over the second gate insulating layer, wherein the second thin film transistor comprises: a first insulating layer; a second oxide semiconductor layer over the first insulating layer; a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer; a third gate insulating layer over the second oxide semiconductor layer, the second source electrode layer, and the second drain electrode layer; and a third gate electrode layer over the third gate insulating layer, wherein the first drain electrode layer is electrically connected to the second source electrode layer, and wherein the third gate electrode layer is electrically connected to the second source electrode layer. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein an off-current value in each of the first thin film transistor and the second thin film transistor is less than or equal to 1×10−13 A. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×1019 atoms/cm3, and wherein a carrier concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×1014/cm3. ### Claim 11 (depends on 8) The semiconductor device according to claim 8, wherein a channel length of the first thin film transistor is longer than a channel length of the second thin film transistor. ### Claim 12 (depends on 8) The semiconductor device according to claim 8, wherein a thickness of the first oxide semiconductor layer is smaller than a thickness of the second oxide semiconductor layer. ### Claim 13 (depends on 8) The semiconductor device according to claim 8, wherein the semiconductor device is a CPU. ### Claim 14 (depends on 8) The semiconductor device according to claim 8, wherein the semiconductor device is an LSI. ### Claim 15 (depends on 8) The semiconductor device according to claim 8, wherein the semiconductor device is a DRAM. ### Claim 16 (depends on 8) The semiconductor device according to claim 8, wherein the semiconductor substrate is set to a fixed potential or a ground potential.