US 8,421,068 B2 · Semiconductor device and manufacturing method thereof

Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Claims14

Dependent claims

A semiconductor device comprising:

a substrate having an insulating surface;
a first gate electrode layer over the substrate;
a first electrode layer over the substrate;
a first gate insulating layer over the first gate electrode layer and the first electrode layer;
an oxide semiconductor layer over the first gate insulating layer;
a first insulating layer over the first electrode layer;
a source electrode layer and a drain electrode layer over the oxide semiconductor layer;
a second gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
and
a second gate electrode layer over the second gate insulating layer,
wherein at least part of the drain electrode layer overlaps with the first electrode layer, and
wherein the first insulating layer and the first gate insulating layer are provided between the drain electrode layer and the first electrode layer.

9 more elements

A semiconductor device comprising an EDMOS circuit comprising:

a substrate having an insulating surface;
a first thin film transistor over the substrate;
and
a second thin film transistor over the substrate,
wherein the first thin film transistor comprises:
a first gate electrode layer;
a first gate insulating layer over the first gate electrode layer;
an first oxide semiconductor layer over the first gate insulating layer;
a first source electrode layer and a first drain electrode layer over the first oxide semiconductor layer;
a second gate insulating layer over the first oxide semiconductor layer, the first source electrode layer, and the first drain electrode layer;
and
a second gate electrode layer over the second gate insulating layer,
wherein the second thin film transistor comprises:
a first insulating layer;
a second oxide semiconductor layer over the first insulating layer;
a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer;
a third gate insulating layer over the second oxide semiconductor layer, the second source electrode layer, and the second drain electrode layer;
and
a third gate electrode layer over the third gate insulating layer,
wherein the first drain electrode layer is electrically connected to the second source electrode layer, and
wherein the third gate electrode layer is electrically connected to the second source electrode layer.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/904,565Filed 14 Oct 2010

Priority

JP 2009-23888516 Oct 2009

Published

US 2011/0089414 A121 Apr 2011

Granted

16 Apr 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10D 30/6706
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device: for…
G06K 19/07758
The record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card:…
H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Semiconductor device and manufacturing method thereof

Life of this patent

Semiconductor device and manufacturing method thereof

Life of this patent

Abstract

Claims14