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US 8,413,163 B2Granted
Program control device including per-timeslot switching of thread execution
AssigneePanasonic Corporation
InventorKunihiko Hayashi
Life of this patent
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Abstract
Provided is a program control device which switches, per timeslot, between threads to be executed. The program control device includes: a first interrupt creation unit which creates a first interrupt signal which designates a timeslot as a destination; and a first receiving unit which [i] does not receive the first interrupt signal if the timeslot as the destination is not a current timeslot, and [ii] receives the first interrupt signal if the timeslot as the destination is the current timeslot.
Claims21
A program control device which switches, per timeslot, between threads to be executed, said program control device comprising:
- a plurality of processors;
- an interrupt creator configured to cause a first processor to create a first interrupt signal that contains information which designates, as a destination, timeslot assigned to one of the first processor and a second processor, the first processor and the second processor being included in the plurality of processors, the second processor being different than the first processor;
- a receiver configured to control one of the first processor and the second processor assigned with the timeslot designated as the destination, in the information contained in the first interrupt signal, not to receive the first interrupt signal if the timeslot designated as the destination in the information is not a current timeslot and to receive the first interrupt signal if the timeslot is the current timeslot;
- a storage in which thread information regarding a thread and timeslot information regarding a timeslot are stored, the thread information including an identifier of a timeslot to which the thread is allocated, and the timeslot information including information indicating a thread which is allocated to the timeslot;
- a specifier configured to specify the timeslot as the destination of the first interrupt signal, based on the thread information and the timeslot information,
- wherein said interrupt creator is configured to create the first interrupt signal which designates, as the destination, the timeslot specified by said specifier;
- a receive processor configured to receive a system call from a current thread which is being executed in the current timeslot;
- a scheduler configured to change one of a state of a thread and a state of a timeslot in response to the system call, the thread and the timeslot being included among threads and timeslots including the current thread and the current timeslot, respectively,
- a first dispatcher configured to switch between threads to be executed in the timeslot as the destination, in response to the first interrupt signal received by said receiver;
- and
- a second dispatcher configured to change the timeslot information regarding a thread in response to the second interrupt signal received by said receiver, the thread being included among threads including the thread relating to the change;
- wherein said interrupt creator is configured:
- when said scheduler changes the state of the thread, to create the first interrupt signal which designates, as the destination, a timeslot to which a thread relating to the change is allowed, the thread relating to the change being included among threads including the thread with the state being changed by said scheduler,
- when said scheduler changes the state of the timeslot, to create a second interrupt signal.
11 more elements
A program control device which switches, per timeslot, between threads to be executed, said program control device comprising:
- a plurality of processors;
- an interrupt creator configured to cause a first processor to create a first interrupt signal that contains information which designates, as a destination, a timeslot assigned to one of the first processor and a second processor, the first processor and the second processor being included in the plurality of processors, the second processor being different than the first processor;
- a receiver configured to control one of the first processor and the second processor assigned with the timeslot designated as the destination in the information contained in the first interrupt signal, not to receive the first interrupt signal if the timeslot designated as the destination in the information is not a current timeslot and to receive the first interrupt signal if the timeslot is the current timeslot;
- wherein said program control device is included in a multi-processor including said plurality of processors,
- said interrupt creator, which is provided for each of the plurality of processors, is configured to create the first interrupt signal which designates one of the plurality of processors and the timeslot as the destination, and
- said receiver, which is provided for each of the plurality of processors, is configured not to receive the first interrupt signal, if the processor for which said receiver is provided is not the processor designated in the first interrupt signal, and to receive the first interrupt signal, if the processor for which said receiver is provided is the processor designated in the first interrupt signal,
- said program control device further comprises:
- a thread information storage in which thread information for each thread is stored, the thread information including a state of a corresponding thread and an identifier of a timeslot to which the corresponding thread is allocated;
- a timeslot information storage in which timeslot information for each timeslot is stored, the timeslot information including an allocation time allocated for a corresponding timeslot, information designating a thread allocated to the corresponding timeslot, and an identifier of a processor to which the corresponding timeslot is allocated;
- a receive processor, which is included in each of the plurality of processors, and is configured to receive a system call from a current thread which is being executed in the current timeslot;
- and
- a scheduler, which is included in each of the plurality of processors, and is configured to change one of the thread information and the timeslot information, in response to the system call received by said receiver,
- wherein said interrupt creator includes:
- a first interrupt creator, which is included in each of the plurality of processors, and is configured to create the first interrupt signal which designates a processor as a processor destination and the timeslot as the destination, when said scheduler in the processor including said first interrupt creator changes the thread information, and
- a second interrupt creator, which is included in each of the plurality of processors, configured to create a second interrupt signal which designates a processor as a processor designation, when said scheduler in the processor including said second interrupt creator changes the timeslot information.
12 more elements
Dependencies are inferred from the claim text.