Transaction level model synthesis
AssigneeSynopsys, Inc.
InventorSerge Goossens
Life of this patent
Estimating the term…
Abstract
Converting from transaction level model to register transfer level. A method comprises accessing a transaction level model description. Function calls in the transaction level model description are automatically converted to signal accesses in a register transfer level description. Interlace logic is automatically generated in the register transfer level description. The interface logic provides an interface between a bus interface and the signal accesses. The register transfer level description is stored in a computer readable medium.
Claims34
A computer implemented method comprising:
- a) accessing a transaction level model description of an integrated circuit;
- re-writing the transaction level model description into a synthesizable subset of the transaction level model description including a communication portion comprising timing information and a behavioral portion wherein the communication portion and the behavior portion of the transaction level model description are separate so that the communication portion can be synthesized independently;
- b) automatically converting function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description;
- c) automatically generating interface logic in the synthesizable subset of the register transfer level description, said interface logic, comprising an interface between a bus interface and the signal accesses, wherein the interface logic includes combinational logic of a signal generator and butler registers, wherein the buffer registers are modeled as clock methods and the combination logic is modeled as a method sensitive to its inputs, and wherein buffer registers are inferred and one or more buffer registers store protocol content to implement a cross-reference to another transfer belonging to a same transaction;
- and
- d) storing the register transfer level description including said signal accesses and said interface logic between said bus interface and said signal accesses in a computer readable medium.
A system comprising a processor coupled to a computer readable medium via a bus, wherein said computer readable medium comprises instructions that when executed by said processor implement a method of converting from a transaction level model description to a register transfer level description, said method comprising:
- a) accessing a transaction level model description of an integrated circuit;
- re-writing the transaction level model description into a synthesizable subset of the transaction level model description including a communication portion comprising timing information and a behavioral portion wherein the communication portion and the behavior portion of the transaction level model description are separate so that the communication portion can be synthesized independently;
- b) automatically converting application program interface (API) calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description, wherein said signal accesses have substantially the same semantics as the API calls;
- c) automatically generating interface logic in the synthesizable subset of the register transfer level description, said interface logic comprising an interface between a bus interface of the register transfer level description and the signal accesses, wherein the interface logic, includes combinational logic of a signal generator and buffer registers, wherein the buffer registers are modeled as clock methods and the combination logic is modeled as a method sensitive to its and wherein buffer registers are inferred and one or more buffer registers store protocol content to implement a cross-reference to another transfer belonging to a same transaction;
- and
- d) storing said register transfer level description including said signal accesses and said interface logic between said bus interface and said signal accesses in said computer readable medium.
A computer readable medium having stored thereon instructions that when executed on a processor implement a method of convening from a transaction level model to a register transfer level, said method comprising:
- a) accessing a transaction level model description of an integrated circuit;
- re-writing the transaction level model description into a synthesizable subset of the transaction level model description including a communication portion comprising timing information and a behavioral portion wherein the communication portion and the behavior portion of the transaction level model description are separate so that the communication portion can be synthesized independently;
- b) automatically convening function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description;
- c) automatically generating interface logic in the synthesizable subset of the register transfer level description said interface logic providing an interface between a bus interface and the signal accesses, wherein the interface logic includes combinational logic of a signal generator and buffer registers, wherein the buffer registers are modeled as clock methods and the combination logic is modeled as a method sensitive to its inputs, and wherein buffer registers are inferred and one or more buffer registers store protocol content to implement a cross-reference to another transfer belonging to a same transaction;
- and
- d) storing the register transfer level description including said signal accesses and said interface logic between said bus interface and said signal accesses in said computer readable medium.
Dependencies are inferred from the claim text.