US 8,413,102 B2 · Vectorless IVD analysis prior to tapeout to prevent scan test failure due to voltage drop

Abstract

In one embodiment, a vectorless IVD methodology may be used to estimate IVD issues for an integrated circuit earlier in the design cycle of the integrated circuit, e.g. when corrective actions may still be taken to correct IVD failures. In the methodology, scan chains for various clusters in the integrated circuit may be identified, even though the scan chains may still be subject to change as the design evolves. A power integrity tool may analyze the scan chains based on a probability of transitions in the devices within the scan chain (e.g. flops) for a theoretical worst-case test vector. If the result of analysis identifies IVD failures in the clusters, corrective action may be taken such as modifying the design. Alternatively, the corrective action may include identifying one or more flops that experience failure as devices to be excluded from the test vector generation process for scan testing.

Claims12

Dependent claims

A method comprising:

receiving a design description of an integrated circuit and a description of one or more scan chains in the integrated circuit, each scan chain comprising a serial connection of clocked storage devices, the serial connection formed by connecting scan in inputs and scan out outputs of the clocked storage devices;
assigning probabilities to each possible state transition for each clocked storage device in the one or more scan chains based on a scan test pattern of alternating binary one and binary zero values, wherein the scan test pattern is serially shifted through the scan chains during a scan test using the serial connection;
responsive to the probabilities and the design description, identifying instance voltage drop (IVD) failures the would occur during scan testing in the integrated circuit, wherein the IVD failures are identified prior to tapeout of the integrated circuit;
identifying a plurality of clocked storage devices that experience the IVD failures;
and
excluding the plurality of clocked storage devices during scan test pattern generation by an automated test pattern generation tool.

3 more elements

Dependencies are inferred from the claim text.

Vectorless IVD analysis prior to tapeout to prevent scan test failure due to voltage drop

Life of this patent

Vectorless IVD analysis prior to tapeout to prevent scan test failure due to voltage drop

Life of this patent

Abstract

Claims12