Statistical single library including on chip variation for rapid timing and power analysis

A computer-implemented method for creating a statistical single worst case (WC) library, using a Liberty model, and including on-chip variation (OCV), said method comprising:

• receiving, by a computer, libraries for all cells of a digital chip design including ranges for supply voltage, input load, input slew, and temperature parameters, and any of chip mean and OCV process, aging, and N/P mistrack parameters;
• applying, by said computer, a statistical model created for statistical timing to said ranges for supply voltage, input load, input slew, and temperature parameters, and said any of chip mean process, aging, and N/P mistrack parameters;
• applying, by said computer, a statistical timing tool across said ranges for supply voltage, input load, input slew, and temperature parameters, and said any of chip mean process, aging, and N/P mistrack parameters to determine WC statistical corners for delay and power to said all cells for selected input loads from said input load range and selected input slews from said input slew range;
• entering, by said computer, said delay and said power to said all cells, for each of said WC statistical corners, associated with each selected input load and each selected input slew, into said statistical single WC library.