Circuit design supporting apparatus and circuit design supporting method

A circuit design supporting apparatus comprising:

• an observation portion specifying section configured to specify a first portion of an integrated circuit as an observation portion, the first portion determined to have an effect on an easiness of a failure analysis of the integrated circuit;
• and
• an element substitution performing section configured to substitute an element arranged in said observation portion with an analysis target element so that a failure analysis apparatus is better able to conduct said failure analysis based on data derived from said observation portion,
• wherein said observation portion specifying section extracts equivalent failure groups G1 to GI (I is an integer equal to or more than 1) of failures which failure points cannot be specified in the integrated circuit by external measurement, from a netlist,
• wherein a parameter Di (i=1 to I) to said equivalent failure group Gi is defined by Di=JiPi, where a number of nets which are contained in said equivalent failure group Gi is Ji, and a probability that a failure is contained in said equivalent failure group Gi is Pi, and
• wherein a summation of said parameters Di is defined as an analysis difficulty degree M, and a decrease rate of said analysis difficulty degree M through an insertion of the observation portion is defined as an analysis easiness improvement effect, and a point where said observation portion is inserted based on the analysis easiness improvement effect is a position of said observation portion.

A circuit design supporting method comprising:

• specifying, by an observation portion specifying section, as executed by a processor on a computer, a first portion of an integrated circuit as an observation portion, the first portion determined as having an effect on an easiness of a failure analysis of the integrated circuit;
• and
• substituting, by an element substitution performing section, an element arranged in said observation portion with an analysis target element so that data derived from said observation portion by a failure analysis apparatus is improved, thereby improving the easiness to conduct said failure analysis of said integrated circuit,
• wherein said substituting an element arranged in said observation portion comprises:
• performing a timing analysis of the integrated circuit shown by a netlist;
• calculating a delay in the integrated circuit based on a result of the timing analysis and said netlist;
• specifying a fine element, which is arranged in said observation portion, of elements of the integrated circuit as a substitution candidate element;
• and
• updating said netlist to form a new netlist,
• wherein said calculating a delay comprises calculating a delay change, when substituting said element arranged in said observation portion by with said analysis target element,
• wherein said specifying a fine element comprises generating an instruction to said element substituting section to substitute said substitution candidate element by with said analysis target element, if said delay change when said substitution candidate element is substituted by said analysis target element is within a preset timing margin, and
• wherein said updating comprises forming said new netlist by substituting said substitution candidate element with said analysis target element in response to said instruction from said substitution element determining section.

A non-transitory computer-readable recording medium in which a computer-executable program code is stored to realize a circuit design supporting method, the computer-executable program code, when executed by a computer, performs the circuit design supporting method comprising:

• specifying, by an observation portion specifying section, a first portion of an integrated circuit as an observation portion, the first portion being determined as having an effect on an easiness of a failure analysis of the integrated circuit;
• and
• substituting, by an element substitution performing section, an element arranged in said observation portion with an analysis target element so that data derived from said observation portion by a failure analysis apparatus is improved, thereby improving the easiness to conduct said failure analysis,
• wherein said substituting an element arranged in said observation portion comprises:
• performing a timing analysis of the integrated circuit shown by a netlist;
• calculating a delay in the integrated circuit based on a result of the timing analysis and said netlist;
• specifying a fine element, which is arranged in said observation portion, of elements of the integrated circuit as a substitution candidate element;
• and
• updating said netlist to form a new netlist,
• wherein said calculating a delay comprises calculating a delay change when substituting said element arranged in said observation portion by said analysis target element,
• wherein said specifying a fine element comprises generating an instruction to said element substituting section to substitute said substitution candidate element with said analysis target element, if said delay change when said substitution candidate element is substituted by said analysis target element is within a preset timing margin, and
• wherein said updating comprises forming said new netlist by substituting said substitution candidate element with said analysis target element in response to said instruction from said substitution element determining section.