Pseudorandom binary sequence checker with control circuitry for end-of-test check
AssigneeAgere Systems Inc.
InventorsSi Ruo Chen, Hao Li, Jin Song Liu, Tao Wang
Life of this patent
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Abstract
Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.
Claims21
An apparatus comprising:
- a pseudorandom binary sequence (PRBS) checker having a data input and an error event output;
- and
- control circuitry coupled between the error event output and the data input of the PRBS checker;
- the control circuitry being configured to switch between a first operating state in which a received PRBS signal from a design under test is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker, wherein the error signal is applied to the data input of the PRBS checker independent of a PRBS signal from the design under test.
A method comprising the steps of:
- applying a received PRBS signal from a design under test to a data input of a PRBS checker;
- detecting a designated condition of the PRBS checker;
- and
- responsive to detection of the designated condition, applying an error signal to the data input of the PRBS checker, wherein the error signal is applied to the data input of the PRBS checker independent of a PRBS signal from the design under test.
A testing system comprising:
- a pseudorandom binary sequence (PRBS) generator configured to generate a PRBS signal for transmission to a design under test;
- a PRBS checker configured to receive the PRBS signal from the design under test and having a data input and an error event output;
- and
- control circuitry coupled between the error event output and the data input of the PRBS checker;
- the control circuitry being configured to switch between a first operating state in which the received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker, wherein the error signal is applied to the data input of the PRBS checker independent of a PRBS signal from the design under test.
Dependencies are inferred from the claim text.