Methods, apparatus, and systems for updating loglikelihood ratio information in an nT implementation of a Viterbi decoder
AssigneeLSI Corporation
InventorsBrian K. Gutcher, Kripa Venkatachalam
Life of this patent
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AssigneeLSI Corporation
InventorsBrian K. Gutcher, Kripa Venkatachalam
Estimating the term…
Methods and circuits comprising a reliability measurement unit (RMU) for generating log-likelihood ratio (LLR) values corresponding to 1T for use in a soft output Viterbi algorithm (“SOVA”) decoder. The RMU operates with an nT clock signal. 1T signals generated by an add, compare, select circuit (ACS) of the SOVA generates 1T decision data and a path equivalency detector generates 1T path equivalency information for 1T SOVA decoding and applies the 1T data to the RMU operating with an nT clock frequency (1/n'th that of the 1T clock signal). The nT RMU receives a plurality of 1T inputs on each nT clock signal pulse and generates 1T LLR information for use by the SOVA decoder. Other components of the SOVA may also operate using the nT clock signal pulse or may operate using a 1T clock signal.
A method for generating 1T log-likelihood ratio (LLR) values from an nT reliability measurement unit (RMU) in a soft output Viterbi algorithm (SOVA) decoder where n is greater than 1, the method comprising:
A circuit usable in conjunction with a soft output Viterbi algorithm (SOVA) decoder, the SOVA decoder operable to generate 1T signals as inputs to the circuit, the circuit comprising:
Dependencies are inferred from the claim text.