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US 8,413,018 B2Granted
Separate memories and address busses to store data and signature
AssigneeBrocade Communications Systems, Inc.
InventorsKung-Ling Ko, Surya Prakash Varanasi, Subbarao Palacharla
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Abstract
A programmable device employs an address and data corruption logic for data written to a first memory. A first signature is computed from the data stored in the first memory and stored in a second memory. When data is read from the first memory, the first signature stored in the second memory is read and compared with a second signature computed from the data read from the first memory. If the first and second signatures do not match, an error condition is indicated.
Claims19
A device, comprising:
- a first memory;
- a second memory;
- a core logic unit, coupled to the first memory via a first address line and coupled to the second memory via a second address line, wherein the core logic unit is programmed to read from and write to the first and second memories;
- a first signature generator logic, configured to compute a first signature from data written to the first memory, coupled to the second memory to store the first signature in the second memory;
- a second signature generator logic, configured to compute a second signature from data read from the first memory;
- and
- a comparator logic, coupled to the second memory and the second signature generator logic, indicating an error condition to the core logic unit if the first signature does not match the second signature
- wherein the first signature is computed as part of writing to the first memory.
5 more elements
A method, comprising:
- comparing a first signature computed from data written to a first memory using a first address line with a second signature computed from data read from the first memory;
- and
- storing the first signature in a second memory using a second address line,
- wherein the first signature is computed as part of writing to the first memory.
1 more element
A device comprising:
- a first memory;
- and
- a field programmable gate array (FPGA), coupled to the first memory using a first address line, the FPGA comprising:
- a second memory, internal to the FPGA, addressed using a second address line;
- and
- logic to perform the acts of:
- comparing a first signature computed from data written to the first memory with a second signature computed from data read from the first memory;
- and
- storing the first signature in the second memory,
- wherein the first signature is computed as part of writing to the first memory.
7 more elements
Dependencies are inferred from the claim text.