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US 8,413,015 B2Granted
Nonvolatile memory controller with scalable pipelined error correction
AssigneeSanDisk Technologies LLC
InventorsSteven S. Cheng, Aruna Gutta
Life of this patent
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Abstract
A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.
Claims12
A removable nonvolatile memory system comprising:
- a first nonvolatile memory chip;
- a second nonvolatile memory chip;
- a controller chip that has a first memory interface in communication with the first memory chip and a second memory interface in communication with the second memory chip, the first memory interface connected to a first Error Correction Coding (“ECC”) block that is dedicated to the first memory interface, and the second memory interface connected to a second ECC block that is dedicated to the second memory interface;
- a host interface that is in communication with both the first ECC block and the second ECC block;
- and
- a first clock signal that is provided to the first ECC block and the second ECC block;
- and
- a second clock signal that is provided to the host interface, the second clock signal having a higher frequency than the first clock signal.
5 more elements
A method of performing error correction in a removable nonvolatile memory system comprising:
- receiving a first stream of encoded data from a first nonvolatile memory chip in the removable nonvolatile memory system;
- providing the first stream of encoded data to a first Error Correction Coding (“ECC”) block on a controller chip in the removable nonvolatile memory system;
- decoding the first stream of data in the first ECC block to obtain a first stream of decoded data;
- providing the first stream of decoded data to a host interface of the removable nonvolatile memory system;
- receiving a second stream of encoded data from a second nonvolatile memory chip in the removable nonvolatile memory system;
- providing the second stream of encoded data to a second ECC block on the controller chip;
- decoding the second stream of data in the second ECC block to obtain a second stream of decoded data;
- providing the second stream of decoded data to the host interface;
- providing a first clock signal to the first ECC block and to the second ECC block;
- and
- providing a second clock signal to the host interface, wherein the second clock signal is a higher frequency clock signal than the first clock signal.
8 more elements
A memory controller comprising:
- a first memory input/output;
- a first Error Correction Coding (“ECC”) block in communication with the first memory input/output;
- a second memory input/output;
- a second ECC block in communication with the second memory input/output;
- a host interface in communication with the first ECC block and the second ECC block a first clock that provides a first clock signal at a first frequency, the first clock signal provided to the first ECC block and to the second ECC block;
- and
- a second clock that provides a second clock signal at a second frequency, the second clock signal provided to the host interface, wherein the second frequency is higher than the first frequency.
4 more elements
Dependencies are inferred from the claim text.