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US 8,413,011 B2Granted
Device and method providing 1-bit error correction
AssigneeSamsung Electronics Co., Ltd.
InventorsYong June Kim, Jae Hong Kim, Jun Jin Kong
Life of this patent
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Abstract
A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.
Claims5
A 1-bit error correction method comprising:
- calculating a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes;
- determining whether a peak number of unsatisfied check nodes calculated with respect to the respective variable nodes exceeds a predetermined value;
- performing error decoding of a bit corresponding to a variable node with respect to which the peak number of unsatisfied check nodes has been calculated when the peak number of unsatisfied check nodes exceeds the predetermined value;
- detecting a position of a first or last one of the variable nodes connected to the unsatisfied check nodes when the peak number of unsatisfied check nodes does not exceed the predetermined value;
- and
- estimating that an error has occurred at a variable node positioned “k” places after the first variable node among the variable nodes connected to the unsatisfied check nodes, or
- estimating that an error has occurred at a variable node positioned “k” places before the last variable node among the variable nodes connected to the unsatisfied check nodes,
- where “k” denotes a message size in a parity-check matrix.
5 more elements
A 1-bit error correction device comprising:
- a computation unit configured to calculate a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes;
- a control unit configured to determine whether a peak number of unsatisfied check nodes calculated by the computation unit exceeds a predetermined value;
- and
- an error correction unit configured to perform error correction of a bit corresponding to a variable node with respect to which the peak number of unsatisfied check nodes has been calculated when the peak number of unsatisfied check nodes exceeds the predetermined value,
- wherein the control unit is further configured to detect a position of a first or last one of the variable nodes connected to the unsatisfied check nodes when the peak number of unsatisfied check nodes does not exceed the predetermined value and the error correction unit performs error correction based on the detected position of the first or last variable node,
- wherein the error correction unit is further configured to correct an error in a bit corresponding to a variable node positioned “k” places after the first variable node among the variable nodes connected to the unsatisfied check nodes or corrects an error in a bit corresponding to a variable node positioned “k” places before the last variable node among the variable nodes connected to the unsatisfied check nodes, where “k” denotes a message size in a parity-check matrix, and
- wherein at least one of the computation unit, the control unit and the error correction unit comprises a processor configured to respectively perform the calculation, the determination and the error correction.
4 more elements
Dependencies are inferred from the claim text.